Single-phase Inverter Application Research Articles

A modified SOGI-FLL algorithm with DC-offset rejection improvement for single-phase inverter applications

A modified SOGI-FLL algorithm with DC-offset rejection improvement for single-phase inverter applications

A High Power Density Multilevel Bipolar Active Single-Phase Buffer With Full Capacitor Energy Utilization and Controlled Power Harmonics

Active power decoupling in single-phase conversion systems reduces the required capacitance for twice-line frequency power ripple buffering by operating the energy buffering capacitors with high energy utilization ratios. The bipolar active buffer is the buffer topology that can achieve 100% energy utilization ratio. Yet, the conventional two-level full-bridge designs suffer from high switching and conduction loss and large filter inductor size due to the direct connection of the buffer across the high voltage dc-bus. Moreover, the high voltage swings across the buffer capacitor impose challenges for the control to regulate harmonics in the system. This article improves the power density and the efficiency of the bipolar active buffer through a buffer architecture incorporating the flying capacitor multilevel topology. Moreover, control techniques to regulate harmonics in the buffer are proposed to maintain low ripple in the dc-side current. The use of two common types of capacitors, the metal film capacitor and the X6S multilayer ceramic capacitor (MLCC) as buffer capacitors, is addressed with different harmonic control schemes. With MLCCs, we have also achieved a total passive component volume that is almost three times smaller than state-of-the-art solutions. The proposed approach is validated using a compact hardware for a 2-kW, 400-V dc-bus, 60-Hz single-phase inverter application.

Instantaneous Pulse Power Compensator for High-Density Single-Phase Inverters

In this paper, instantaneous pulse power compensator (IPPC) method is proposed to achieve power pulsation decoupling function for single-phase inverter applications. A smaller capacitor is placed in series with the traditional dc-link capacitor, and this smaller capacitor voltage is controlled using pulse currents to cancel out the dc-link voltage ripple. Unlike twice-line-frequency power decoupling method, the proposed IPPC method can compensate the pulsating power with all the orders harmonics on the dc-link line, not only the second-order component. Both modeling and simulation results show that IPPC method can achieve nearly zero voltage ripple for the dc-link capacitor since the pulse current is fully compensated. Whereas twice-line-frequency power decoupling method has limit in voltage ripple reduction, especially in small dc-link capacitance conditions. The experimental results based on a full-bridge topology decoupling circuit and a single-phase inverter application show consistent results with simulation results. A 16% reduction of the prototype size, i.e., 16% higher power density with only ∼1% efficiency penalty can be achieved by the proposed IPPC method when compared to the second-order power decoupling method.

New Constraint in SHE-PWM for Single-Phase Inverter Applications

This paper proposes new angles constraint for selective harmonic elimination-pulsewidth modulation (SHE)-PWM utilized in single-phase inverter applications. The proposed angles constraint naturally eliminates all triplen harmonics, whereas they conventionally appeared in all single-phase output voltages. The harmonic amplitude formula is developed based on the obtained angles constraint, and then modified single-phase SHE equations are defined to eliminate only specified low nontriplen harmonics. Therefore, more harmonics would be eliminated with the same switching frequency in modified SHE-PWM. Five-level voltage waveform has been opted to implement the introduced method, but it can be applied on all multilevel voltage waveforms such as seven-level with even number of angles. Unlike the conventional SHE technique, THD is analyzable in modified SHE to find optimum values for switching angles in order to control noneliminated harmonic amplitudes and minimize THD. Moreover, the cancellation of triplen harmonics empowers a single-phase inverter to supply nonlinear loads beside linear ones. Some experimental tests are accomplished using a single-phase five-level modified packed U-cell (MPUC) inverter. Results are discussed to prove the excellent performance of a single-phase MPUC inverter under both normal and harmonic loads and accurate elimination of determined triplen and nontriplen harmonics by applying the presented angles constraint.

Capacitor impedance estimation utilizing dc‐link voltage oscillations in single phase inverter

Grid tied single-phase solar inverters offer less operational life when compared with the Photovoltaic (PV) panels due to the use of aluminium electrolytic capacitor (AEC). With time, AEC degrades, resulting in an increase in ripple voltage on PV panel. This would reduce the power extraction efficiency of the system, thereby a loss of revenue. This study proposes a simple and cost-efficient online technique for monitoring the health of AECs. The proposed technique suggests evaluating the AEC impedance at twice the grid frequency. Sampling of PV voltage, PV current and inductor current is required to determine the second harmonic impedance of AEC. These voltage and current sensors are present in commercially available solar PV inverters for their control operation. The proposed technique could be extended to other single-phase inverter applications provided that voltage and current sensors are available. Suitable mathematical model of the technique is derived to determine the effect of sampling instant on the accuracy of the results. Criteria for the replacement of capacitor based on impedance monitoring is defined. For validation of the proposed technique, detailed simulation studies are carried out for a single-phase PV system. The technique is verified experimentally on a scaled down solar PV inverter prototype.