Single Memory Module Research Articles

Multi-Temporal Ultra Dense Memory Network for Video Super-Resolution

Video super-resolution (SR) aims to reconstruct the corresponding high-resolution (HR) frames from consecutive low-resolution (LR) frames. It is crucial for video SR to harness both inter-frame temporal correlations and intra-frame spatial correlations among frames. Previous video SR methods based on convolutional neural network (CNN) mostly adopt a single-channel structure and a single memory module, so they are unable to fully exploit inter-frame temporal correlations specific for video. To this end, this paper proposes a multi-temporal ultra-dense memory (MTUDM) network for video super-resolution. Particularly, we embed convolutional long-short-term memory (ConvLSTM) into ultra-dense residual block (UDRB) to construct an ultra-dense memory block (UDMB) for extracting and retaining spatio-temporal correlations. This design also reduces the layer depth by expanding the width, thus avoiding training difficulties, such as gradient exploding and vanishing under a large model. We further adopt multi-temporal information fusion (MTIF) strategy to merge the extracted temporal feature maps in consecutive frames, improving the accuracy without requiring much extra computational cost. The experimental results on extensive public datasets demonstrate that our method outperforms the state-of-the-art methods by a large margin.

Multi-Memory Convolutional Neural Network for Video Super-Resolution.

Video super-resolution (SR) is focused on reconstructing high-resolution (HR) frames from consecutive lowresolution (LR) frames. Most previous video SR methods based on convolutional neural network (CNN) use a direct connection and single-memory module within the network, and they thus fail to make full use of spatio-temporal complementary information from LR observed frames. To fully exploit spatio-temporal correlations between adjacent LR frames and reveal more realistic details, this paper proposes a multi-memory convolutional neural network (MMCNN) for video SR, cascading an optical flow network and an image-reconstruction network. A serial of residual blocks engaged in utilizing intra-frame spatial correlations are proposed for feature extraction and reconstruction. Particularly, instead of using single-memory module, we embed convolutional long short-term memory (ConvLSTM) into the residual block, thus form a multi-memory residual block to progressively extract and retain inter-frame temporal correlations between consecutive LR frames. We conduct extensive experiments on numerous testing datasets with respect to different scaling factors. Our proposed MMCNN shows superiority over the state-of-the-art methods in terms of PSNR and visual quality and surpasses the best counterpart method 1 dB at most. The code and datasets are available at https://github.com/psychopa4/MMCNN.

Latency- and hazard-free volume memory architecture for direct volume rendering

Real-time direct volume rendering (ray-casting or volume ray-tracing) is achieved by problem specific rendering architectures. The performance of these architectures is however limited by the access to the volume memory. Although many different volume memory architectures have been proposed and realized, none of them uses the read-out-gain provided by new DRAM interfaces like Rambus-DRAM, SDRAM etc. In this paper a solution is presented that allows profit from these new interfaces. The key feature of the new architecture is a multi-level cache system with software prefetching and latency hiding. By allowing the rendering pipeline processor to operate at up to 200 MHz, a 512 3 data set stored in a single memory module can be rendered at 3.125 Hz. An even higher performance is possible from the DRAM side but is limited by current SRAM and processor speeds.

Performance analysis of the FFT algorithm on a shared-memory parallel architecture

This paper presents a model for the performance prediction of FFT algorithms executed on a shared-memory parallel computer consisting of N processors an the same number of memory modules. The model applies a deterministic analysis to estimate the communication delay through the interconnection network by assuming that all requests arrive at the network in bursts. Our results indicate that the communication delay is significantly affected by the method applied to allocate data to memory modules. For the case in which all data items referenced by a processor during an iteration are allocated to a single memory module, the best-case communication time complexity grows as O[(log N) 2 /N]. The worst-case communication time complexity for this case, obtained by a different allocation of data to memory modules, is increased to O[(log N)/√N] due to high network contention. For the case in which the data items referenced by different processors during an iteration are allocated to the same memory module, the communication time complexity is further increased to O(log N) since all N requests generated by processors are serialized at a single memory module. The methods developed in this paper can be applied for the performance prediction of other well-structured parallel iterative algorithms.