Single-layer Routing Research Articles

Via-Avoidance-Oriented Interposer Routing for Layer Minimization in 2.5-D IC Designs

It is well known that interposer-based 2.5-D integrated circuit (IC) designs have become one of the most promising solutions for providing yield improvement, enhancing system performance, decreasing power consumption, and supporting heterogeneous integration. In this article, given a set of nets including some inter-chip or through-silicon buses between chips and package, inside a silicon interposer, a via-avoidance-oriented routing algorithm can be proposed to minimize the number of the used layers by satisfying the noncrossing constraint between two nets and the constraint of using no via on the inter-chip sub-nets and no vertical detour on the through-silicon sub-nets in multiple-layer interposer routing. The routing process in our proposed algorithm can be divided into two sequential steps: iterative routing step and refinement step. In the iterative routing step, the routing process of all the given nets can be completed for layer minimization in a top-down layer-by-layer manner. In each iteration, based on the definition of the obstacle-aware routing pattern for the inter-chip sub-net on one given net, the assignment of the obstacle-aware routing patterns can be firstly obtained in single-layer routing. Furthermore, the routing paths of some inter-chip sub-nets and the partial or full routing paths of some through-silicon sub-nets can be assigned and routed onto the available layer by using a maze routing process under the detour constraints. In the refinement step, based on the routing result of the given nets on the used layers, the detoured inter-chip or through-silicon sub-nets can be firstly reassigned and rerouted for the detour reduction of the given nets. Furthermore, a set of zigzag paths can be inserted onto some nets inside the given inter-chip or through-silicon buses for skew minimization. Compared with the combination of the iterative routing using Cadence’s automatic router and the detouring-path insertion on the number of the used layers, the experimental results show that our proposed routing algorithm can use reasonable CPU time and shorter wirelength to decrease 19.3% of the number of the used layers for eight tested examples on the average.

Modified swarm algorithm «ant tree» in the problem of diversification of tractor resources spaces

In this work, the problem of increasing traceability is solved by diversifying trace resources, which consists in using additional areas adjacent to the channels below and above, with a trace layer located above the “over-the-cell” cells. For a single-layer routing uses a new paradigm of combinatorial optimization – ant tree (trees ant colony optimization (T-ACO)), based on the ideas of adaptive behavior of ant colony. The decision tree is used as a decision search graph. An agent for the decision search graph does not create a route, but a tree, which in its structure coincides with the representation of the solution to the trace problem in the «over-the-cell» region. This eliminates the use of additional transformations in the decoding process of decisions that allow interpretation of decisions in the form of trees and allows you to discard a lot of «illegal» solutions, which leads to an increase in the quality of the solutions obtained. Using the tracing procedure in «over-the-cell» based on the ant algorithm allows you to unload the channel by 15-20%. The time complexity of the algorithm depends on the number of vertices n of the decision search graph, the number of agents y, the number of iterations l, and is defined as O (n2·l·y).

Single-Layer Obstacle-Aware Substrate Routing via Iterative Pin Reassignment and Wire Assignment

It is known that single-layer obstacle-aware substrate routing is necessary for modern IC/Package designs. In this article, given a set of two-pin nets and a set of rectangular obstacles inside a single-layer routing plane, a two-phase routing algorithm including an iterative routing phase and a rip-up-and-reroute phase can be proposed to maximize the number of the routed nets in single-layer obstacle-aware substrate routing. In the iterative routing phase, based on the pin and path distribution of the routing nets and the locations of the obstacles inside a single-layer routing plane, the start or target pins on some routing nets inside dense obstacle regions may be firstly reassigned to complete the partial wiring paths on the nets. Based on the region extraction of two intersected nets in single-layer routing, the private regions of some routing nets inside sparse obstacle regions can be extracted and the nets inside the extracted regions can be further routed by using maze routing. In the rip-up-and-reroute phase, the routability of the routing nets can be improved by ripping up some routed nets and rerouting the unrouted nets. Compared with Liu's modified algorithm and Yan's flow-based algorithm in single-layer obstacle-aware substrate routing, the experimental results show that the proposed algorithm can use less CPU time to increase 3.4% and 1.8% of the routability on the routing nets for eight tested examples on the average. Additionally, the percentage of the tested examples with the 100% routability of the routing nets on the eight tested examples has been improved from 25% to 62.5%.

Single-Layer GNR Routing for Minimization of Bending Delay

As feature sizes in semiconductor technique scale down, traditional CMOS devices and interconnects are facing several challenges. Graphene nanribbon (GNR)-based devices and interconnects can be treated to be better alternative in nano-scale designs. In this paper, given a set of nets in a single-layer GNR routing (SGNRR) plane, an efficient routing algorithm can be proposed to maximize the number of the routed nets with minimizing the bending delay in SGNRR. The routing process in our proposed algorithm can be divided into three sequential steps: 1) routability-driven net assignment; 2) iterative diffusion-based transformation for delay reduction; and 3) iterative rip-up-and-reroute (IRUR) for delay reduction. In routability-driven net assignment, based on the transformation of multiple-pin nets and the region extraction of two intersected nets in single-layer routing, some detored nets can be selected and the remaining nets can be first routed inside their available regions. Furthermore, the detored nets can be routed by using single-layer obstacle-aware routing. In iterative diffusion-based transformation for delay reduction, the available empty space in an initial routing result can be further used to transform 120° bends into 60° bends. In IRUR process for delay reduction, the routing order of two adjacent nets may be further exchanged to reduce the bending delay if empty space is available. Compared with the combination of the transformation of multiple-pin nets and Yan's negotiated congestion-based algorithm in SGNRR, the experimental results show that our proposed algorithm can use less CPU time to decrease 11.1% of total bending delay with increasing 1.3% of total wirelength on the given nets with the same 100% routability for six tested examples on the average. Additionally, the experimental results show that our proposed algorithm can use less CPU time to increase 5.5% of routability on the given nets for six denser examples on the average.

MULTILAYER INTEGRATED ROUTING IN PACKET AND OPTICAL NETWORKS

In telecommunication networks, the most common solution for routing problems is the decoupling of the routing for every layer. This approach however can provide a sub-optimal solution wherein the routing at the packet layer becomes independent of the optical layer routing. Thus, in order to address this issue, a multilayer integrated routing for packet and optical networks is considered. In this paper, we consider multilayer integrated routing in packet and optical networks. For multilayer integrated routing, we consider both interlayer traffic and network information together. Researchers have generally been investigating only single-layer routing problems such as packet layer routing, and optical layer routing. Considering only one-layer routing leads to a sub-optimal solution in terms of the entire network. However, as we consider both packet and optical layers routing together, we try to optimize network usage in both layers. To achieve this goal we formulate mathematical models with various objective functions and constraints. To solve the mathematical models, linear programming and integer programming solution techniques can be applied. However, for large size in-tiger programming models, the problems are NP-complete. Therefore, we recommend a heuristic algorithm to solve such problems. Finally, we use several examples to confirm the performance of the mathematical models.

Routing in Vehicular Ad-hoc Networks: A Survey on Single- and Cross-Layer Design Techniques, and Perspectives

Vehicular ad-hoc networks (VANETs) play an important role in intelligent transportation systems for improving security and efficiency. However, due to dynamic characteristics of the vehicular environment, routing remains a significant challenge in the VANETs. While single-layer routing protocols based on the traditional layered open systems interconnection (OSI) model are readily available, they often do not make use of important parameters at the lower three layers of the OSI model when making routing decision. Hence, for making optimal routing decision to gain superior network performance, there is a need to design cross-layer routing that allows information exchange between layers. In this article, a survey of the existing single-layer and cross-layer routing techniques in VANETs is presented, emphasizing on cross-layer routing protocols that utilize information at the physical, medium access control and network layers as routing parameters. An overview and challenges of routing are given, followed by a brief discussion of single-layer routing with more focus on geographic routing. Cross-layer routing protocols are then discussed in detail. The article then elaborates on some advantages and disadvantages of the existing routing approaches, cross-layer routing parameter selection and cross-layer design issues. Finally, some open research challenges in developing efficient routing protocols in the VANETs are highlighted.

Моделирование однослойных и двухслойных трассировок

Моделирование однослойных и двухслойных трассировок

Sharp Switching by Field-Effect Bandgap Modulation in All-Graphene Side-Gate Transistors

Graphene is a 2-D electronic material that has drawn intensive interest due to its high carrier mobility, film flexibility, and tunable bandgap. The unique bandgap modulation by the transverse electrical field in the graphene nanoribbon (GNR) offers new opportunity to pursue switches with steep subthreshold not limited by thermal voltage. In this paper, we demonstrate a graphene routing process (GRP), which can implement the side-gate GNR transistor with field-effect bandgap modulation (FEBM). The GRP precisely aligns the side gates to the transistor channel, and provides scalable W/L without registry concerns. Besides, by controlling the pattern sizing, the metallic source/drain, side gates, and semiconducting channel are all defined on the large-area graphene thin-film by one-critical lithography step. The GRP process thus can be adapted to the backend process with thin-film transfer even on flexible substrates. The double side-gate GNR transistors exhibit FEBM and a negative temperature coefficient for the ON-state conductance which can stabilize thermal runaway. In addition, the single-layer routing for simple circuit topology can improve package density and reduce number of contact vias. Combining FEBM with the electrostatic control can bring forth higher ON current and sub-60 mV/decade switching. These device characteristics offer a potential power-gating technology in low-power applications.

Active and passive component embedding into low-cost plastic substrates aimed at smart system applications

The technology development for a low-cost, roll-to-roll compatible chip embedding process is described in this paper. Target applications are intelligent labels and disposable sensor patches. Two generations of the technology are depicted. In the first version of the embedding technology, the chips are embedded in an adhesive layer between a copper foil and a PET film. While this results in a very thin (< 200 μm) and flexible system, the single-layer routing and the incompatibility with passive components restricts the application of this first generation. The double-sided circuitry embedding technology is an extension of the single-sided, foil-based chip embedding, where the PET film is replaced by a second metal foil. To obtain sufficient mechanical strength and to further reduce cost, the adhesive film is replaced by a substrate material which is compatible with the chip embedding concept. Both versions of the foil-based embedding technology are very versatile, as they are compatible with a broad range of polymer materials, for which the specifications can be tuned to the final application.

CAFE Router: A Fast Connectivity Aware Multiple Nets Routing Algorithm for Routing Grid with Obstacles

Due to the increase of operation frequency in recent LSI systems, signal propagation delays are required to achieve specifications with very high accuracy. In order to achieve the severe requirements, signal propagation delay is taken into account in the routing design of PCB (Printed Circuit Board). In the routing design of PCB, the controllability of wire length is often focused on since it enables us to control the routing delay. In this paper, we propose CAFE router which obtains routes of multiple nets with target wire lengths for single layer routing grid with obstacles. CAFE router extends the route of each net from a terminal to the other terminal greedily so that the wire length of the net approaches its target wire length. Experiments show that CAFE router obtains the routes of nets with small length error in short time.

Optimal river routing with crosstalk constraints

With the increasing density of VLSI circuits, the interconnection wires are being packed even closer. This has increased the effect of interaction among these wires on circuit performance and hence, the importance of controlling crosstalk. In this article, we consider river routing with crosstalk constraints. Given the positions of the pins in a single-layer routing channel and the maximum tolerable crosstalk between each pair of neighboring nets, we give a polynomial time algorithm to decide whether there is a feasible river routing solution and produce one with minimum crosstalk when it is feasible.

Correction to "Boundary single-layer routing with movable terminals"

In boundary single-layer routing with slidable or permutable terminals (BSLR-S or BSLR-P), the assumption that each net may have more than one terminal in a range or cluster should be removed. An example that shows Pick-Closest might report "unsolvable" for a solvable instance is considered. It is clear that the instance is solvable if (and only if) the two terminals of net N/sub 1/ are assigned to vertices c and d. However, Pick-Closest will assign the two terminals of net N/sub 1/ to vertices /spl lcub/b,c/spl rcub/ or /spl lcub/d,e/spl rcub/, then report "unsolvable" due to the failure in routing net N/sub 2/. Thus, Pick-Closest only works in instances when each net has at most one terminal in a range. Since BSLR-P also includes slidable terminals, we employ Pick-Closest to solve BSLR-P when TR-permutation is determined by Greedy-Assignment. Thus in BSLR-P, each net can have at most one terminal in a cluster as well. The time complexity of the problem of boundary single-layer routing with slidable and permutable terminals remains open if a net is allowed to have multiple terminals in a cluster.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

M/sup 2/R: multilayer routing algorithm for high-performance MCMs

We introduce a new multilayer routing strategy for high-performance MCMs whose objective is to route all nets optimizing routing performance and to satisfy various design constraints (e.g., minimizing coupling between vias as well as between signal lines and minimizing discontinuities such as vias and bends). First we introduce the Pin Pre-wiring and Redistribution Problem, which redistributes the pins or prewired subnets uniformly over the MCM substrate using pin redistribution layers. Pin redistribution is very important in MCM design. Our experience shows that it not only provides a global distribution for the pins congested in the chip site over the chip layer so as to ease the future routing difficulty, but also reduces the capacitive coupling between vias induced by many layers (up to 63 layers) by separating the pins far apart. The goal of the problem is to minimize the number of layers required to redistribute the entire set. An effective approach is proposed for solving this problem. Next we develop four effective algorithms for signal distribution, i.e., two variations on both single-layer routing and xy plane-pair routing paradigms. Based on these algorithms, a mixed version of single-layer routing and xy plane-pair routing techniques is proposed to establish a good trade-off between them to favor circuit performance and/or design objective instead of overemphasizing on the area minimization. One strategy is to apply single-layer routing iteratively until /spl alpha/ % of the nets are routed, then route the remaining (100/spl minus//spl alpha/)% nets by xy plane-pair routing process. This provides the designer with a trade-off (e.g., between the number of layers and total number of vias) and shows the versatility of the proposed techniques. Various strategies are compared using practical MCM examples (each MCM has 25-100 ICs, 25-60 I/Os per IC, and 50-1,200 nets).< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Minimum separation for single-layer channel routing

We present a linear-time algorithm for determining the minimum height of a single-layer routing channel. The algorithm handles single-sided connections and multiterminal nets. It yields a simple routability test for single-layer switchboxes, correcting an error in the literature.

PLANAR ROUTING AROUND A RECTANGLE

The problem of planar (single-layer) routing, of two- and multi-terminal nets, around a rectangle is considered. Necessary and sufficient conditions for the existence of a solution is presented. An O(n) time algorithm for obtaining a minimum-area planar routing, if one exists, is proposed, where n is the number of terminals.

Planar topological routing of pad nets

This paper discusses the problem of single-layer topological routing of pad nets. A pad net is one that connects a set of module pins to a pad on the boundary of the chip. An important application arises in VLSI designs with many different power sources, in which case there may be multiple power and ground nets to be routed on a single layer. We present an O( n) algorithm for checking the feasibility of a single-layer routing of pad nets, and an O( m × n) algorithm for constructing a planar topological routing, where n is the total number of pad-net pins on all the modules, and m is the number of modules. The feasibility algorithm exploits the special structure of the problem, and is based on a distribution sorting technique rather than being a general planarity checking algorithm. The topological routing algorithm first forms a chain of the modules, and then performs a permutation routing of the nets using the chain as a guide.

Boundary single-layer routing with movable terminals

The authors study a generalization of previous results on the boundary single-layer routing (BSLR) problem. In the BSLR problem, there is a planar graph, a collection of terminals on the boundary of the infinite face, and a set of multiterminal nets. A solution of BSLR consists of a set of vertex disjoint trees interconnecting the terminals belonging to the same (multiterminal) net. An algorithm, unifying and generalizing previous BSLR algorithms, to solve an arbitrary instance of BSLR, is presented. Problems involving slidable terminals (i.e. when terminals can slide within a certain range on the boundary) and permutable terminals (i.e. when positions of some terminals (going to the same gate) can be interchanged) are optimally solved. The proposed algorithm runs in O(e) time, where e is the number of edges in the input graph. The results are extended to handle gridless routing environments.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Unconstrained via minimization for topological multilayer routing

A theoretical study which allows determination of the minimum number of vias for realizable multilayer channel routing under a topological model is presented. The theory is sufficiently general to solve a variety of problems under different technological constraints, e.g. VLSI multilayer switchbox and channel routing, through-hole printed circuit board (PCB) channels, and single-layer routing. Topological routing is concerned with wire intersection but not area, zero-width wires and zero-area vias being assumed. Unconstrained via minimization (UVM) is not constrained to a prerouted topology. This paper presents restrictive cases of UVM, finding most to be NP-hard, but the case resulting from constraints of traditional switchbox or channel routing to be solvable in O(kn/sup 2/), where k is the maximum number of pins of a net layer and n is the number of pins. The minimum number of vias for various switchbox and channel routing benchmarks are reported.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A hexagonal array machine for multilayer wire routing

A novel hardware accelerator comprised of several fast processors interconnected in the form of a hexagonal mesh with wraparound connections is proposed. The novelty of the proposed architecture stems from the fact that it is suitable not only for single-layer routing, but also for routing in parallel on multiple layers. A hexagonal machine of dimension square root kG, with about 3kG processors, can handle a k-layer grid consisting of kG/sup 2/ grid points at about the same speed as a full-grid machine with kG/sup 2/ processors. A technique for measuring the performance of a hardware accelerator in terms of the average delay incurred over a full-grid machine is suggested. This has been formalized in the case of the hexagonal architecture, and is presented for various nets and mesh dimensions. The results have been accurately verified by extensive simulation done in C++ language. It is demonstrated that the hexagonal mesh, by virtue of its additional links for expansion, is resilient to about 10% of failure in the links and processing elements. A detailed design for a chip implementation of the hexagonal machine is discussed. >

Pad Assignment for Power Nets in VLSI Circuits

This paper deals with the problem of single layer routing of power nets in building-block-style layout. It is assumed that power-supplying terminals are placed on the boundary of the chip and that each module within the chip has to be supplied by two or three different sources. The problem considered here is how to assign the power pads on the boundary of the chip so that their number is minimum while maintaining the planar routability of the power nets.