Single Instruction Stream-multiple Data Stream Research Articles

A General CPL-AdS Methodology for Fixing Dynamic Parameters in Dual Environments

The algorithm of Continuous Point Location with Adaptive d-ary Search (CPL-AdS) strategy exhibits its efficiency in solving stochastic point location (SPL) problems. However, there is one bottleneck for this CPL-AdS strategy which is that, when the dimension of the feature, or the number of divided subintervals for each iteration, d is large, the decision table for elimination process is almost unavailable. On the other hand, the larger dimension of the features d can generally make this CPL-AdS strategy avoid oscillation and converge faster. This paper presents a generalized universal decision formula to solve this bottleneck problem. As a matter of fact, this decision formula has a wider usage beyond handling out this SPL problems, such as dealing with deterministic point location problems and searching data in Single Instruction Stream-Multiple Data Stream based on Concurrent Read and Exclusive Write parallel computer model. Meanwhile, we generalized the CPL-AdS strategy with an extending formula, which is capable of tracking an unknown dynamic parameter λ in both informative and deceptive environments. Furthermore, we employed different learning automata in the generalized CPL-AdS method to find out if faster learning algorithm will lead to better realization of the generalized CPL-AdS method. All of these aforementioned contributions are vitally important whether in theory or in practical applications. Finally, extensive experiments show that our proposed approaches are efficient and feasible.

New Reconfigurable Memory Architecture for Parallel Image-Processing LSI with Three-Dimensional Structure

A reconfigurable memory network for a parallel image-processing LSI with a three-dimensional structure is proposed. The proposed memory network can be dynamically configured by changing the connections between processing elements (PEs) and memories in accordance with the required part of the stored image data. In addition, a specification of the data bandwidth between PEs and the proposed memory network can be changed in the synchronization with single instruction stream-multiple data stream (SIMD) and multiple instruction stream-multiple data stream (MIMD) operations. Therefore, data transfer has greater flexibility. Also, from the result of the performance evaluation by implementation into the field programmable gate array (FPGA), it was successfully shown that the proposed memory network reduced the execution time by up to 28.2% for a 9×9 filtering operation.

Fractally-Structured CMOS Processor for Quantum-Circuit Emulation

A novel complementary-metal-oxide-semiconductor (CMOS) processor labelled quantum-circuit processor (QCP) for the high-performance emulation of quantum computing is presented. The QCP performs the emulation of the calculation performed in the quantum circuit by simple matrix calculations based on single-instruction-stream-multiple-data-stream (SIMD) parallel processing. Using the parallel operation of an enormous number of devices in LSI, it executes quantum algorithms at a speed comparable to that of the quantum computer. A 5-qubit processor was implemented using a programmable logic device (PLD), and the quantum Fourier transformation was demonstrated by this processor.

Parallel (M−N)SVD algorithms on the SIMD computers

LetA bem byn matrix,M andN be positive definite matrices of orderm andn respectively. This paper presents an efficient method for computing (M−N) singular value decomposition ((M−N) SVD) ofA on a cube connected single instruction stream-multiple data stream (SIMD) parallel computer. This method is based on a one-sided orthogonalization algorithm due to Hestenes. On the cube connected SIMD parallel computer witho(n) processors, the (M−N)SVD of a matrixA requires a computation time ofo(m3logm/n).

Fault-tolerant reconfigurable architecture for robot kinematics and dynamics computations

Efficient parallel algorithms for computing the kinematics, dynamics, and Jacobian of manipulators and their corresponding inverses are discussed and analyzed, and their characteristics are identified based on the type and degree of parallelism, uniformity of the operations, fundamental operations, data dependencies, and communication requirements. Most of the algorithms for robotic computations possess highly regular properties and some common structures, especially the linear recursive structure. They are well-suited to be implemented on a single-instruction-stream-multiple-data-stream (SIMD) computer with reconfigurable interconnection networks. A reconfigurable dual-network SIMD machine with internal direct feedback that best matches these characteristics has been designed. To achieve high efficiency in the computation of robotics algorithms on the proposed parallel machine, a generalized cube interconnection network is proposed. A centralized network switch control scheme is developed to support the pipeline timing of this machine. To maintain high reliability in the overall system, a fault-tolerant generalized cube network is designed to improve the original network. >

Process groups and group communications: classifications and requirements

An attempt is made to place recent architectural innovations in the broader context of parallel architecture development by surveying the fundamentals of both newer and more established parallel computer architectures and by placing these architectural alternatives in a coherent framework. The primary emphasis is on architectural constructs rather than specific parallel machines. Three categories of architecture are defined and discussed: synchronous architectures, comprising vector, SIMD (single-instruction-stream, multiple-data-stream) and systolic machines; MIMD (multiple-instruction-stream, multiple-data-stream) with either distributed or shared memory; and MIMD-based paradigms, comprising MIMD/SIMD hybrid, dataflow, reduction, and wavefront types. >

Odd even shifts in SIMD hypercubes

A linear-time algorithm is developed to perform all odd (even) length circular shifts of data in an SIMD (single-instruction-stream, multiple-data-stream) hypercube. As an application, the algorithm is used to obtain an O(M/sup 2/+log N) time and O(1) memory per processor algorithm to compute the two-dimensional convolution of an N*N image and an M*M template on an N/sup 2/ processor SIMD hypercube. This improves the previous best complexity of O(M/sup 2/ log M+log N). >

Connection autonomy in SIMD computers: A VLSI implementation

Fine-grain SIMD (single instruction stream-multiple data stream) parallel architectures exhibit very high performance in a variety of application fields (such as vision, scientific computing, geometric modeling, and artificial intelligence) mainly because of the massive data parallelism. It is, however, desirable to increase the autonomy of the SIMD architecture for further efficiency. For example, with operation autonomy different processors are able to execute different operations, while with address autonomy, each processor can fetch data from memory locations different from the other processors. Because of the quantity (i.e., tens of thousands) and the simplicity (e.g., bit-serial) of the processors in fine-grain SIMD system, these autonomies may be too expensive to justify their benefits. Nevertheless, one type of autonomy, connection autonomy, is extremely beneficial and is economic in VLSI implementation. We investigate connection autonomy for fine-grain SIMD parallel architecture in this paper by showing a model for connection autonomy, the utilization of connection autonomy, and its VLSI implementation. The architecture and the instruction set of the YUPPIE system (Yorktown ultra parallel polymorphic image engine) are presented and some programming examples are given. We show that, by adding 20% silicon area over each processor, connection autonomy can deliver orders of magnitude of performance improvement over the same network without connection autonomy.

Simulation of a word recognition system on two parallel architectures

The use of two parallel architectures, a single-instruction-stream, multiple-data-stream (SIMD) machine and a VLSI processor array, to implement an isolated word recognition system is examined. SIMD and VLSI processor array algorithms are written for each of the components of the recognition system. The component parallel algorithms are simulated along with two complete recognition systems, one composed of SIMD algorithms and other composed of VLSI processor array algorithms. The simulations show that a SIMD machine with 100 processing elements, each based on an 8-MHz MC68000, can perform isolated word recognition over a large vocabulary in real time. The VLSI processor array simulations show that an array using 51 cells, each containing a 12-MHz Intel 8051, can recognize speech in real time over a small vocabulary. The simulation revealed certain architectural features that can enhance the overall performance of the speech system.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

SIMD architectures and algorithms for image processing and computer vision

The authors present a critical survey of parallel architectures and algorithms for image processing. The emphasis is on single-instruction-stream, multiple-data-stream (SIMD) computers with nonshared memory. A number of parallel architectures are discussed and compared. They fall into three categories: mesh-connected computers, pyramid computers, and hypercube and related computers. A set of seven image processing and computer vision tasks is selected, and algorithms for performing these seven tasks on each of the three categories of computers are given. All of the algorithms are evaluated using asymptotic (big-Oh) analysis. An analysis of parallel algorithms for several-pixel level, intermediate level, and high-level image processing tasks is presented. The effects of architectural decisions on algorithms design are examined in detail.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Efficient parallel algorithms and VLSI architectures for manipulator Jacobian computation

The real-time computation of the Jacobian that relates the manipulator joint velocities to the linear and angular velocities of the manipulator end-effector is pursued. Since the Jacobian can be expressed in the form of a first-order linear recurrence, the time lower bound for computing the Jacobian can be proved to be of order O(N) on uniprocessor computers and of order O(log/sub 2/ N) on both single-instruction-stream-multiple-data-stream (SIMD) and VLSI pipelined parallel processors, where N is the number of links of the manipulator. To achieve the lower bound, the authors developed a generalized-k method for uniprocessor computers, a parallel forward and backward recursive doubling algorithm (PFABRD) for SIMD computers, and a parallel systolic architecture for VLSI pipelines. All the methods are capable of computing the Jacobian at any desired reference coordinate frame k from the base coordinate frame to the end-effector coordinate frame. The computational effort in terms of floating-point operations is minimal when k is in the range (4,N-3) for the generalized-k method, and k=(N+1)/2 for both the PFABRD algorithm and the parallel pipeline.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Alternating group explicit (AGE) iterative methods

In this paper the Alternating Group Explicit (AGE) methods, modified analogues of the classical Alternating Direction Implicit (ADI) methods, are introduced. Their explicit nature and their obvious parallelism, in contrast with the inherent parallelism of the ADI methods, makes them most suitable for the solution of the resulting linear systems arising from the discretisation of a class of elliptic PDEs on a Parallel Computer of SIMD (Single Instruction Stream-Multiple Data Stream) type. The determination of optimum sets of acceleration parameters in 2-dimensional problems is discussed and numerical experiments are successfully completed.

Augmenting Ada for SIMD Parallel Processing

In order to program SIMD (single instruction stream-multiple data stream) parallel machines used for tasks such as speech and image processing, a language with explicit parallel constructs is often desirable. The language Ada, developed by the Department of Defense, is used here as a basis for such a language. Extensions of Ada, which allow the user to specify such operations as interprocessor communications and activation of processors, are proposed. These features are demonstrated by showing their use in a common speech processing algorithm, the parallel FFT.

SIMD Image Resampling

Due to advances in VLSI technology, large scale arrays of microprocessors forming parallel processing systems have become feasible. The use of such a microprocessor array operating in the SIMD (single instruction stream-multiple data stream) mode to perform image resampling is explored. A general theory of resampling in terms of offsets is developed. From this, an approach to performing resampling in an SIMD environment is given. Detailed analysis of the SIMD algorithm is presented, and computational speedup over conventional uniprocessor approaches is shown to be approximately a factor of N where N is the number of processors used.

A Model of SIMD Machines and a Comparison of Various Interconnection Networks

A formal mathematical model of single instruction stream-multiple data stream (SIMD) machines is defined. It is used as a basis for analyzing various types of interconnection networks that have been discussed in the literature. The networks are evaluated in terms of the lower and upper bounds on the time required for each of the networks discussed to simulate the other networks. SIMD machine algorithms are presented as proofs of the upper time bounds on these simulation tasks. These simulations are used to demonstrate techniques for proving the correctness of SIMD machine algorithms, i.e., analyzing the simultaneous flow of N data items among N processors. Processor address masks, a concise notation for activating and deactivating processors, are used in the algorithms. The methods used to prove the lower bounds and to construct (and prove correct) simulation algorithms to show the upper bounds can be generalized and applied to the analysis of other networks.

Very high-speed computing systems

Very high-speed computers may be classified as follows: 1) Single Instruction Stream-Single Data Stream (SISD) 2) Single Instruction Stream-Multiple Data Stream (SIMD) 3) Multiple Instruction Stream-Single Data Stream (MISD) 4) Multiple Instruction Stream-Multiple Data Stream (MIMD). Stream, as used here, refers to the sequence of data or instructions as seen by the machine during the execution of a program. The constituents of a system: storage, execution, and instruction handling (branching) are discussed with regard to recent developments and/or systems limitations. The constituents are discussed in terms of concurrent SISD systems (CDC 6600 series and, in particular, IBM Model 90 series), since multiple stream organizations usually do not require any more elaborate components. Representative organizations are selected from each class and the arrangement of the constituents is shown.