Single Input Signature Registers Research Articles

A fast signature computation algorithm for LFSR and MISR

A multiple-input signature register (MISR) computation algorithm for fast signature simulation is proposed. Based on the table look-up linear compaction algorithm and the modularity property of a single-input signature register (SISR), some new accelerating schemes-partial-input look-up tables and flying state look-up tables-are developed to boost the signature computation speed. Mathematical analysis and simulation results show that this algorithm has an order of magnitude speedup without extra memory requirement compared with the original linear compaction algorithm. Though this algorithm is derived for SISR, a simple conversion scheme exists that can convert internal-EXOR MISR to SISR. Consequently, fast MISR signature computation can be done.

On the maximum value of aliasing probabilities for single input signature registers

The aliasing error performance of a signature register is measured by the maximum values of the aliasing error probabilities for certain ranges of the bit-error rate (and those of the test length). Based on these measures, we evaluate the performances of all the single input signature registers whose feedback polynomials are primitive polynomials of degree 16 and generator polynomials of the double-error-correcting BCH codes of the same degree. When the degree of the feedback polynomial is large, say 32, it is computationally hard to obtain the exact aliasing probability. But we observe that the numbers of codewords with large weights in the corresponding code dominate the maximum value of the aliasing probabilities. By computing the numbers of codewords of large weights, we find primitive polynomials of degree 32 whose maximum value of the aliasing probabilities is very large for some test lengths. The error performance of an LFSR with any BCH polynomial of degree m for the test length 2/sup m/2/-2 is shown to be very good by deriving the formula for the weight distribution of the corresponding code. >

Shrinking wide compressors [BIST

Quite often built-in self-test (BIST) designs make use of multiple-input signature registers (MISR's) to compress the test data. Normally a MISR includes a stage for every signal that it is sampling. In some applications this leads to very wide MISR's that may include several hundred stages. Wide MISR's pose problems in terms of hardware and wiring overhead. Shorter compressors are, therefore, needed. This paper investigates the problem of shrinking an MISR so that it samples multiple signals at every stage. The ultimate shrinkage occurs when only the parity of the sampled signals is compressed. This is the case when a MISR is replaced by a single-input signature register (SISR). Issues like detection probability loss, test length penalty, and fault coverage degradation are some of the disadvantages that may arise from the MISR shrinkage. Minimizing the effect of these issues is a precondition to the success of this method.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>