Single-grain Si Thin-film Transistors Research Articles

Single-grain Si thin-film transistors on flexible polyimide substrate fabricated from doctor-blade coated liquid-Si

Solution process of silicon will provide high-speed transistor fabrication with low-cost by, for example, roll-to-roll process. In this paper, a low-temperature process (350 °C) is reported for fabrication of high-quality Si devices on a polyimide substrate from doctor-blade coated liquid-Si. With this method, different semiconductor devices have been fabricated, reporting a carrier mobility of 460 cm2/V s and 121 cm2/V s for electrons and holes, respectively. The devices were peeled off and transferred onto a polyethylene naphthalate foil to achieve flexible devices. CMOS inverters were also fabricated and show full output swing.

Single-grain Si thin-film transistors SPICE model, analog and RF circuit applications

Single-grain thin-film transistors (SG-TFTs) fabricated inside location-controlled using μ-Czochralski process exhibit SOI-FETs like performance despite processing temperatures remaining below 350°C. Thus, the SG-TFT is a potential technology for large-area highly-integrated electronic system and system-in-package, taking advantage of the system-on-flexible substrate and low manufacturing cost capabalities. The SG-TFT is modeled based on the BSIMSOI SPICE model where the mobility parameter is modified to fit the SG-TFT behavior. Therefore, analog and RF circuits can be designed and benchmarked. A two-stage telescopic cascode operational amplifier fabricated in a prototype 1.5μm SG-TFT technology demonstrates DC gain of 55dB and unity-gain bandwidth of 6.3MHz. A prototype CMOS voltage reference demonstrates a power supply rejection ratio (PSRR) of 50dB. With unity-gain frequency, fT, in the GHz range, the SG-TFT can also enable RF circuits for wireless applications. A 12dB gain RF cascode amplifier with integrated on-chip inductors operating in the 433MHz ISM band is demonstrated.

Single-Grain Si TFTs and Circuits Inside Location-Controlled Grains Fabricated Using a Capping Layer of $\hbox{SiO}_{2}$

To enlarge the size of two-dimensional location-controlled Si grains fabricated in the mu-Czochralski process in excimer-laser crystallization, a capping layer (C/L) of SiO2 was applied to the amorphous-Si (a-Si) thin film. With a 50-nm-thick SiO2 C/L on a 100-nm-thick a-Si film, the diameter of the location-controlled grain was increased to 7.5 mum. Single-grain Si thin-film transistors (TFTs) were fabricated with the SiO2 C/L as part of the gate insulator. Field-effect mobilities of 510 and 210 cm2/Vmiddots were obtained for electrons and holes, respectively. Both TFTs were integrated in a single-grain CMOS inverter inside a location-controlled grain. The propagation gate delay was found to be shorter than that in poly-Si circuits under the same device conditions