Single-Grain Si TFTs and Circuits Inside Location-Controlled Grains Fabricated Using a Capping Layer of $\hbox{SiO}_{2}$

Abstract

To enlarge the size of two-dimensional location-controlled Si grains fabricated in the mu-Czochralski process in excimer-laser crystallization, a capping layer (C/L) of SiO2 was applied to the amorphous-Si (a-Si) thin film. With a 50-nm-thick SiO2 C/L on a 100-nm-thick a-Si film, the diameter of the location-controlled grain was increased to 7.5 mum. Single-grain Si thin-film transistors (TFTs) were fabricated with the SiO2 C/L as part of the gate insulator. Field-effect mobilities of 510 and 210 cm2/Vmiddots were obtained for electrons and holes, respectively. Both TFTs were integrated in a single-grain CMOS inverter inside a location-controlled grain. The propagation gate delay was found to be shorter than that in poly-Si circuits under the same device conditions