Single Field Programmable Gate Array Chip Research Articles

FPGA-Based Real-Time EMTP

Real-time transient simulation of large transmission networks requires significant computational power. This paper proposes a field-programmable gate array (FPGA)-based real-time electromagnetic transient simulator. Taking advantage of the inherent parallel architecture, high density, and high clock speed, the real-time Electromagnetic Transients Program (EMTP) is implemented on a single FPGA chip. It is based on a paralleled algorithm that is deeply pipelined, and uses a floating-point arithmetic calculation to achieve high accuracy for simulating fast electromagnetic transients. To validate the new simulator, a sample system with 15 transmission lines using full frequency-dependent modeling is simulated in real time. A timestep of 12 mus has been achieved based on a 12.5-ns clock period with high data throughput. The captured real-time oscilloscope results demonstrate excellent accuracy of the simulator in comparison to the offline simulation of the original system in the Alternative Transients Program version of EMTP.

Design of a Hardware-Implemented Phase Calculating System for Feedback Control in the LHCD Experiments on EAST

A fully hardware-implemented phase calculating system for the feedback control in the lower-hybrid current drive (LHCD) experiments is presented in this paper. By taking advantages of field programmable gate array (FPGA) chips with embedded digital signal processing (DSP) cores and the Matlab-aided design method, the phase calculating algorithm with a square root operation and parallel process are efficiently implemented in a single FPGA chip to complete the calculation of phase differences fast and accurately in the lower-hybrid wave (LHW) system on EAST.

Effective Uses of FPGAs for Brute-Force Attack on RC4 Ciphers

This paper presents an effective field-programmable gate array (FPGA)-based hardware implementation of a parallel key searching system for the brute-force attack on RC4 encryption. The design employs several novel key scheduling techniques to minimize the total number of cycles for each key search and uses on-chip memories of the FPGA to maximize the number of key searching units per chip. Based on the design, a total of 176 RC4 key searching units can be implemented in a single Xilinx XC2VP20-5 FPGA chip, which currently costs only a few hundred U.S. dollars. Operating at a 47-MHz clock rate, the design can achieve a key searching speed of 1.07 x 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">7</sup> keys per second. Breaking a 40-bit RC4 encryption only requires around 28.5 h.

A field programmable gate array-based ultrasonic spectrometer

This paper describes a novel architecture for a low-voltage ultrasonic data acquisition system intended for process monitoring of liquid chemicals in an industrial context. The system is appropriate for operations in hazardous environments where limits are imposed on the working voltage levels of equipment, due to potential fire or explosion hazards. High SNRs in the captured signal records were achieved using 1 V Golay complementary sequences combined with cross-correlation for signal detection, all of which were implemented on a single-field programmable gate array chip. The system has an operating bandwidth of 40 MHz and a dynamic range at the receiver of 2 Vp-p with a resolution of 14 bits. Theoretical and practical design criteria are examined to optimize received signal SNR and data acquisition rate whilst minimizing hardware complexity. The system was implemented using a reconfigurable hardware platform of relatively low cost, providing a basis for developing more powerful and robust systems in future. Experiments show that the performance of the system is equivalent to that of a conventional high-voltage pulse-transmission system.

FPGA realization of adaptive speed control IC for PMSM drive

This paper presents an adaptive speed control IC for use in a PMSM (Permanent Magnet Synchronous Motor) drive based on FPGA (Field Programmable Gate Array) technology. Firstly, PMSM is mathematics modelled and the vector control scheme is introduced in the current loop of the PMSM drive. Secondly, to increase the performance of the PMSM drive, an AFC (Adaptive Fuzzy Controller) constructed by a fuzzy basis function and a parameter adjustable mechanism is derived and applied to the speed loop of a PMSM drive to cope with the effect of the system dynamic uncertainty and external load. Thirdly, a proposed adaptive speed control IC based on the FPGA is employed to realize the aforementioned current vector controller and adaptive speed controller of PMSM drive. In addition, a FSMD (Finite State Machine with a Datapath) is presented to model the overall AFC algorithm. As a result, a fully digital controller, including the AFC, the current vector scheme, SVPWM (Space Vector Pulse Width Modulation) generation, coordinate transformation and QEP (Quadrature Encoder Pulse) detection, for PMSM drive can be realized within a single FPGA chip. Finally, an experimental system is set up and some experimental results are demonstrated.

Hardware Implementation of a Real-Time Neural Network Controller With a DSP and an FPGA for Nonlinear Systems

In this paper, we implement the intelligent neural network controller hardware with a field programmable gate array (FPGA)-based general purpose chip and a digital signal processing (DSP) board to solve nonlinear system control problems. The designed intelligent control hardware can perform real-time control of the backpropagation learning algorithm of a neural network. The basic proportional-integral-derivative (PID) control algorithms are implemented in an FPGA chip and a neural network controller is implemented in a DSP board. By using a high capacity of an FPGA chip, the additional hardware such as an encoder counter and a pulsewidth modulation (PWM) generator is implemented in a single FPGA chip. As a result, the controller becomes cost effective. It was tested for controlling nonlinear systems such as a robot finger and an inverted pendulum on a moving cart to show performance of the controller

Performance evaluation of an FPGA controlled soft switched inverter

A field programmable gate array (FPGA) based controller is proposed for a dc link series resonant inverter. The basic operation of the zero current switching inverter is briefly described. A strategy of decoupling the control of the dc link current from the load current is identified and referred as decoupled current control (DCC). The use of gate-controlled devices like metal–oxide–semiconductor field-effect transistor/insulated gate bipolar transistor/MOS-controlled thyristor permits a higher resonance frequency at the link of the inverter. The increased frequency enables the application of pulse density modulation technique with a bang–bang controller to synthesise and control the wave-shapes of current and voltage of the inverter. The DCC strategy eliminates the conventional analogue controller. A digital sequence controller has been designed using the state machine technique for the reliable operation of the inverter. The digital design is implemented on a single chip FPGA. To verify the proposed control strategy and the FPGA controller, a prototype has been built and tested. The test results show that a sinusoidal inverter output voltage is maintained with total harmonic distortion less than 5% and a regulation of about 1% from no-load to full-load, including non-linear and transient loads. The performance of the inverter with the FPGA controller is promising and attractive for uninterrupted power supply applications.

PROGRAPE-1: A Programmable, Multi-Purpose Computer for Many-Body Simulations

Abstract We have developed PROGRAPE-1 (PROgrammable GRAPE-1), a programmable multi-purpose computer for many-body simulations. The main difference between PROGRAPE-1 and “traditional” GRAPE systems is that the former uses FPGA (Field Programmable Gate Array) chips as the processing elements, while the latter relies on a hardwired pipeline processor specialized to gravitational interactions. Since the logic implemented in FPGA chips can be reconfigured, we can use PROGRAPE-1 to calculate not only gravitational interactions, but also other forms of interactions, such as the van der Waals force, hydrodynamical interactions in the SPHr calculation, and so on. PROGRAPE-1 comprises two Altera EPF10K100 FPGA chips, each of which contains nominally 100000 gates. To evaluate the programmability and performance of PROGRAPE-1, we implemented a pipeline for gravitational interactions similar to that of GRAPE-3. One pipeline is fitted into a single FPGA chip, operated at 16 MHz clock. Thus, for gravitational interactions, PROGRAPE-1 provided a speed of 0.96 Gflops-equivalent. PROGRAPE will prove to be useful for a wide-range of particle-based simulations in which the calculation cost of interactions other than gravity is high, such as the evaluation of SPH interactions.

An implementation of fuzzy logic controller on the reconfigurable FPGA system

This paper concerns an implementation of a fuzzy logic controller (FLC) on a reconfigurable field-programmable gate array (FPGA) system. In the proposed implementation method, the FLC is partitioned into many temporally independent functional modules, and each module is implemented individually on the FLC automatic design and implementation system, which is an integrated development environment for performing many subtasks such as automatic VHSIC hardware description language description, FPGA synthesis, optimization, placement and routing, and downloading. Each implemented module forms a downloadable hardware object that is ready to configure the FPGA chip. Then, the FPGA chip is consequently reconfigured with one module at a time by using the run-time reconfiguration method. This implementation method is effective when a single FPGA chip cannot fit the FLC due to the limited size of its constituent cells. We test the proposed implementation method by building the FLC for the truck backer-upper control on VCC Corporation's EVC-1 reconfigurable FPGA board directly.

EmGen-a module generator for logic emulation applications

Logic emulation is a technique that uses dynamically reprogrammable systems for prototyping and design verification. Using an emulator, designers can realize designs through a software configuration process and perform real-time design verification before fabricating the chip into silicon. However, converting designs into an emulator involves the use of multiphase design tasks, which is a very time-consuming process. Hence, shortening the time to emulation is always the main concern for the logic-emulation design process. One approach to shorten the design processing time is to replace portions of the design with macro cells. This paper presents a module generator for logic-emulation applications, which is able to generate macro cells of arbitrarily complex functions described in hardware descriptive languages. Furthermore, the module generator can effectively generate a multiple field-programmable gate array (FPGA) macro for large macros that cannot fit in a single FPGA chip. Experiments using the module generator for logic emulation are reported. The results demonstrate that the module generator can effectively and efficiently generate complex macros from their register transfer-level description. In addition, the results also show that the design processing time is significantly shortened when the module generation method is incorporated into the logic-emulation design flow.