Single Field Programmable Gate Array Chip Research Articles

Accurate Multi-Channel QCM Sensor Measurement Enabled by FPGA-Based Embedded System Using GPS

This paper presents a design and implementation proposal for a real-time frequency measurement system for high-precision, multi-channel quartz crystal microbalance (QCM) sensors using a field programmable gate array (FPGA). The key contribution of this work lies in the integration of a frequency measurement and mass resolution computation based on Global Positioning System (GPS) signals within a single FPGA chip, utilizing Input/Output Blocks to incorporate logic QCM oscillator circuits. The FPGA design enables parallel processing, ensuring accurate measurements, faster calculations, and reduced hardware complexity by minimizing the need for external components. As a result, a cost-effective and accurate multi-channel sensor system is developed, serving as a reconfigurable standalone measurement platform with communication capabilities. The system is implemented and tested using the FPGA Xilinx Virtex-6, along with multiple QCM sensors. The implementation on a Xilinx XC6VLX240T FPGA achieves a maximum frequency of 324 MHz and consumes a dynamic power of 120 mW. Notably, the design utilizes a modest number of resources, requiring only 188 slices, 733 flip-flops, and 13 IOBs to perform a double-channel sensor microbalance. The proposed system meets the precision measurement requirements for QCM sensor applications, exhibiting low measurement error when monitoring QCM frequencies ranging from 1 to 50 MHz, with an accuracy of 0.2 ppm and less than 0.1 Hz.

Cost-Effective Network Reordering Using FPGA

The advancement of complex Internet of Things (IoT) devices in recent years has deepened their dependency on network connectivity, demanding low latency and high throughput. At the same time, expanding operating conditions for these devices have brought challenges that limit the design constraints and accessibility for future hardware or software upgrades. These limitations can result in data loss because of out-of-order packets if the design specification cannot keep up with network demands. In addition, existing network reordering solutions become less applicable due to the drastic changes in the type of network endpoints, as IoT devices typically have less memory and are likely to be power-constrained. One approach to address this problem is reordering packets using reconfigurable hardware to ease computation in other functions. Field Programmable Gate Array (FPGA) devices are ideal candidates for hardware implementations at the network endpoints due to their high performance and flexibility. Moreover, previous research on packet reordering using FPGAs has serious design flaws that can lead to unnecessary packet dropping due to blocking in memory. This research proposes a scalable hardware-focused method for packet reordering that can overcome the flaws from previous work while maintaining minimal resource usage and low time complexity. The design utilizes a pipelined approach to perform sorting in parallel and completes the operation within two clock cycles. FPGA resources are optimized using a two-layer memory management system that consumes minimal on-chip memory and registers. Furthermore, the design is scalable to support multi-flow applications with shared memories in a single FPGA chip.

Modulation Method for High-Capacity Fibre Channel Switch and High-Speed Pulse Network Data

Fibre channel (FC) switches are widely used in storage area networks and avionics systems. In this work, the FC protocol, the switching structure and the scheduling algorithm of the FC switch are deeply studied, and a 48-port FC switch is completed on a single-chip field-programmable gate array (FPGA). In addition, an improved scheduling algorithm for Inter-System Link Protocol (iSLP) is proposed for the input and scheduling of optical fiber pulse network data. On this basis, the overall architecture of the FC switch is proposed, the x690tffg1158 FPGA chip is selected, and the FC port control module is designed, which is composed of the receiving controller, the interface state machine, the sending controller, and the flow control. The routing table lookup module of FC switch is designed, the unicast routing table format and multicast routing table format are proposed, and the corresponding unicast and multicast routing table lookup table module architectures are designed. Aiming at the characteristics of high reliability and low distortion in the transmission of high-speed pulse network signals by FC switches, the modulation and demodulation of Bias-T (BIAS-T) are redesigned. The experiment is implemented using Verilog hardware description language (HDL), and Modelsim 10.5 software is adopted to simulate each module of the switch. The switch adopts an 8×N switching structure, which can accurately perform word synchronization. After the link is initialized, the transceivers can send and receive data frames normally. The redesigned BIAS-T is applied to solve the instability of the end of the analog modulation method, and then realize the low distortion and data integrity of the high-speed pulse signal of the FC switch.

A 0.61-μJ/Frame Pipelined Wired-logic DNN Processor in 16-nm FPGA Using Convolutional Non-Linear Neural Network

A pipelined wired-logic deep neural network (DNN) processor implemented in a 16-nm field-programmable gate array (FPGA) is presented. The latency and power required for memory access are minimized by utilizing the wired-logic architecture, thus enabling low power and high throughput operation. One technical issue with the wired-logic architecture is that it requires a lot of hardware resources. To reduce them, two core technologies are developed: (1) a convolutional non-linear neural network (CNNN) and (2) a pipeline-type neuron cell. The CNNN optimizes both the network structure and the non-linear activation function of each neuron by using a newly developed back-propagation-based training method. While conventional reinforcement learning can train only a small size network thus limiting its application to handwritten number recognition, the proposed CNNN enables a larger network size making it applicable to object recognition. The pipeline-type neuron cell has a small look-up table (LUT) to process non-linear functions using only a small amount of hardware resources. These two technologies enable the implementation of the entire network on a single FPGA chip with the wired-logic architecture. Three types of CNNN trained on the CIFAR-10 dataset are implemented in 16-nm FPGAs. An energy efficiency of 0.09, 0.12, and <inline-formula> <tex-math notation="LaTeX">$0.61~\mu \text{J}$ </tex-math></inline-formula>/frame is achieved with 70&#x0025;, 75&#x0025;, and 82&#x0025; accuracy, respectively. Compared with a state-of-the-art accelerator using a binary neural network (BNN), the energy efficiency is improved by more than two orders of magnitude.

FPGA-Embedded Anomaly Detection System for Milling Process

The main goal of this work is to design a supervising controller able to detect an anomaly in the milling process and implement the soultion in Field Programmable Gate Array (FPGA) chip. Executing this task, the controller continuously monitors the vibration signal coming from the acceleration sensor, installed on the milling machine, and striving to isolate new vibration patterns which are different from typical patterns recorded for the correct milling process. The detection method relies on determining selected signal features in the frequency domain and applying an auto-associative neural network (AANN) for novelty detection. It has been shown that by exercising the frequency spectrum of the vibration signal, extracting specific features of the signal’s spectrum, and using an auto-associative neural network, it is possible to detect anomalies in a milling process with relatively high efficiency. The accuracy, sensitivity, specificity, precision, and false alarm rate are equal to 94.3, 100, 91.2, 88.9, and 8.8 percent. All necessary calculations can be accomplished by the developed single-chip FPGA embedded supervising controller. The controller allows high-speed calculations under low power consumption. It characterizes high reliability and low price compared to typically encountered solutions.

A Flexible FPGA-Based Channel Emulator for Non-Stationary MIMO Fading Channels

In this paper, a discrete non-stationary multiple-input multiple-output (MIMO) channel model suitable for the fixed-point realization on the field-programmable gate array (FPGA) hardware platform is proposed. On this basis, we develop a flexible hardware architecture with configurable channel parameters and implement it on a non-stationary MIMO channel emulator in a single FPGA chip. In addition, an improved non-stationary channel emulation method is employed to guarantee accurate channel fading and phase, and the schemes of other key modules are also illustrated and implemented in a single FPGA chip. Hardware tests demonstrate that the output statistical properties of proposed channel emulator, i.e., the probability density function (PDF), cross-correlation function (CCF), Doppler power spectrum density (DPSD), and the power delay profile (PDP) agree well with the corresponding theoretical ones.

Design and Implementation of an Advanced Radar Signal Processor with Waveform Generator and BIST Unit on a Single FPGA Chip

Field Programmable Gate Arrays (FPGAs) are best suited for signal processing applications that require real-time processing. Therefore, it is preferred over DSP processors in implementing radar receivers that processes incoming continuous stream of data. In the past, implementing complex arithmetic operations in floating point representation was a monopoly on DSP processors and the designers had to work around the sequential nature of the DSP processor to make it suitable for real-time applications by using buffered and multi-clocking designs. But nowadays, the great advances in FPGA design technology minimized this design effort since it is capable of performing these complex algorithms in real time. This paper represents the design and implementation of an advanced radar signal processor for binary phase-coded pulsed radar incorporating a time range side lobes suppression technique on a single FPGA chip. The proposed hardware design includes a waveform generator, an advanced signal processing unit, and a built-in self-test (BIST). Design aspects and hardware details for each part is introduced thoroughly.

Shouji: a fast and efficient pre-alignment filter for sequence alignment.

The ability to generate massive amounts of sequencing data continues to overwhelm the processing capability of existing algorithms and compute infrastructures. In this work, we explore the use of hardware/software co-design and hardware acceleration to significantly reduce the execution time of short sequence alignment, a crucial step in analyzing sequenced genomes. We introduce Shouji, a highly parallel and accurate pre-alignment filter that remarkably reduces the need for computationally-costly dynamic programming algorithms. The first key idea of our proposed pre-alignment filter is to provide high filtering accuracy by correctly detecting all common subsequences shared between two given sequences. The second key idea is to design a hardware accelerator that adopts modern field-programmable gate array (FPGA) architectures to further boost the performance of our algorithm. Shouji significantly improves the accuracy of pre-alignment filtering by up to two orders of magnitude compared to the state-of-the-art pre-alignment filters, GateKeeper and SHD. Our FPGA-based accelerator is up to three orders of magnitude faster than the equivalent CPU implementation of Shouji. Using a single FPGA chip, we benchmark the benefits of integrating Shouji with five state-of-the-art sequence aligners, designed for different computing platforms. The addition of Shouji as a pre-alignment step reduces the execution time of the five state-of-the-art sequence aligners by up to 18.8×. Shouji can be adapted for any bioinformatics pipeline that performs sequence alignment for verification. Unlike most existing methods that aim to accelerate sequence alignment, Shouji does not sacrifice any of the aligner capabilities, as it does not modify or replace the alignment step. https://github.com/CMU-SAFARI/Shouji. Supplementary data are available at Bioinformatics online.

A Single-Chip FPGA Holographic Video Processor

In this paper, we present the world's first single-chip field-programmable gate array holographic video processor. It makes 16 computer-generated color holograms of resolution 1920 × 1080 in a second. It uses an off-the-shelf commercial liquid crystral display for the spatial light modulator. To build a single-chip holographic video processor, we used a layer-based computer-generated hologram (CGH) algorithm and a hardware efficient CGH architecture using fixed-point arithmetic. The single-chip holographic video processor provides moving color holograms with low cost, a small footprint, and high energy efficiency. With these characteristics, the holographic video processor will enable the widespread use of holographic applications including mobile and wearable applications.

Implementation, Verification and Validation of an OpenRISC-1200 Soft-core Processor on FPGA

An embedded system is a dedicated computer system in which hardware and software are combined to per-form some specific tasks. Recent advancements in the Field Programmable Gate Array (FPGA) technology make it possible to implement the complete embedded system on a single FPGA chip. The fundamental component of an embedded system is a microprocessor. Soft-core processors are written in hardware description languages and functionally equivalent to an ordinary microprocessor. These soft-core processors are synthesized and implemented on the FPGA devices. In this paper, the OpenRISC 1200 processor is used, which is a 32-bit soft-core processor and written in the Verilog HDL. Xilinx ISE tools perform synthesis, design implementation and configure/program the FPGA. For verification and debugging purpose, a software toolchain from GNU is configured and installed. The software is written in C and Assembly languages. The communication between the host computer and FPGA board is carried out through the serial RS- 232 port.

On-Line Application of SHEM by Particle Swarm Optimization to Grid-Connected, Three-Phase, Two-Level VSCs with Variable DC Link Voltage

This paper is devoted to an otablen-line application of the selective harmonic elimination method (SHEM) to three-phase, two-level, grid-connected voltage source converters (VSCs) by particle swarm optimization (PSO). In such systems, active power can be controlled by the phase shift angle, and reactive power by the modulation index, against variations in the direct current (DC) link voltage. Some selected, low-odd-order harmonic components in the line-to-neutral output voltage waveforms are eliminated by calculating the SHEM angle set continuously through the developed PSO algorithm on field-programmable gate array (FPGA)-based computing hardware as the modulation index is varied. The use of powerful computing hardware permits the elimination of all harmonics up to 50th. The cost function of the developed PSO algorithm is formulated by using an optimum number of particles to obtain a global optimum solution with a small fitness value in each half-cycle of the grid voltage and then updating the SHEM angle set at the beginning of the next full-cycle. Since the convergence of the solution to a global minimum point depends upon the use of correct initial values especially for a large number of SHEM angles, a generalized initialization procedure is also described in the paper. Theoretical results are verified initially using hardware co-simulation. They are also tested using a small scale photovoltaic (PV) supply prototype developed specifically for this purpose. It is demonstrated that the 5th, 7th, 11th, 13th, 17th, and 19th sidekick harmonics are eliminated by on-line calculation of seven SHEM angles through the developed PSO algorithm on a moderately powerful XEM6010-LX150, USB-2.0-integrated FPGA module. All control and protection actions and the calculation of SHEM angles are achieved by a single FPGA chip and its peripherals within the FPGA board.

Field Programmable Gate Arrays Based Real Time Robot Arm Inverse Kinematic Calculations and Visual Servoing

DOI: 10.26650/electrica.2018.49877 Reliability and precision are very important in space, medical, and industrial robot control applications. Recently, researchers have tried to increase the reliability and precision of the robot control implementations. High precision calculation of inverse kinematic, color based object recognition, and parallel robot control based on field programmable gate arrays (FPGA) are combined in the proposed system. The precision of the inverse kinematic solution is improved using the coordinate rotation digital computer (CORDIC) algorithm based on double precision floating point number format. Red, green, and blue (RGB) color space is converted to hue saturation value (HSV) color space, which is more convenient for recognizing the object in different illuminations. Moreover, to realize a smooth operation of the robot arm, a parallel pulse width modulation (PWM) generator is designed. All applications are simulated, synthesized, and loaded in a single FPGA chip, so that the reliability requirement is met. The proposed method was tested with different objects, and the results prove that the proposed inverse kinematic calculations have high precision and the color based object recognition is quite successful in finding coordinates of the objects.

FPGA Implementation of Sensorless Sliding Mode Observer With a Novel Rotation Direction Detection for PMSM Drives

This paper proposes an field programmable gate array (FPGA) implementation of a sensorless controller for surface mounted permanent magnet synchronous machines. Position and speed are both estimated by a sliding mode observer (SMO) which is based on the PMSM stator frame model. The sliding mode manifold is chosen on the real stator current trajetory. In the SMO, a sign function of current error in the feedback correction is adopted. The estimated speed and position are realized on an FPGA controller by COordinate Rotation Digital Computer (CORDIC) algorithm. Using model-based design, with the tools of MATLAB/Simulink and hardware description language coder, the whole control system is designed and implemented in a single FPGA chip. Dedicated hardware optimization algorithms such as pipeline and resource sharing are developed for the implementation as well. The sign function is realized by fully hardware with a relatively high switching frequency. Meanwhile, a fast and practical rotation direction detection method which is based on back electromotive force information is proposed. Experimental results show that the proposed FPGA implemented sensorless SMO for PMSM drives is robust and has high performance.

Agile All-Digital RF Transceiver Implemented in FPGA

This paper presents a new all-digital transceiver architecture fully integrated into a single field-programmable gate array chip. Both the radio frequency (RF) receiver and the transmitter were entirely implemented using a digital datapath from the baseband up to the RF stage without the use of conventional analog-to-digital converter, digital-to-analog converter, or analog mixer. The transmitter chain uses delta-sigma modulation and digital upconversion to produce a two-level RF output signal. The receiver uses a high-speed comparator and pulsewidth modulation to convert the RF signal into a single-bit data stream, which is digitally filtered and then downconverted. Both the transmitter and the receiver are agile with flexible carrier frequency, bandwidth, and modulation capabilities. The transceiver error vector magnitude and the signal-to-noise ratio figures of merit were analyzed in a point-to-point transmission to evaluate the transmitter’s performance. The results show the feasibility of this approach as a more flexible alternative to common radio architectures.

GateKeeper: a new hardware architecture for accelerating pre-alignment in DNA short read mapping.

High throughput DNA sequencing (HTS) technologies generate an excessive number of small DNA segments -called short reads- that cause significant computational burden. To analyze the entire genome, each of the billions of short reads must be mapped to a reference genome based on the similarity between a read and 'candidate' locations in that reference genome. The similarity measurement, called alignment, formulated as an approximate string matching problem, is the computational bottleneck because: (i) it is implemented using quadratic-time dynamic programming algorithms and (ii) the majority of candidate locations in the reference genome do not align with a given read due to high dissimilarity. Calculating the alignment of such incorrect candidate locations consumes an overwhelming majority of a modern read mapper's execution time. Therefore, it is crucial to develop a fast and effective filter that can detect incorrect candidate locations and eliminate them before invoking computationally costly alignment algorithms. We propose GateKeeper, a new hardware accelerator that functions as a pre-alignment step that quickly filters out most incorrect candidate locations. GateKeeper is the first design to accelerate pre-alignment using Field-Programmable Gate Arrays (FPGAs), which can perform pre-alignment much faster than software. When implemented on a single FPGA chip, GateKeeper maintains high accuracy (on average >96%) while providing, on average, 90-fold and 130-fold speedup over the state-of-the-art software pre-alignment techniques, Adjacency Filter and Shifted Hamming Distance (SHD), respectively. The addition of GateKeeper as a pre-alignment step can reduce the verification time of the mrFAST mapper by a factor of 10. https://github.com/BilkentCompGen/GateKeeper. mohammedalser@bilkent.edu.tr or onur.mutlu@inf.ethz.ch or calkan@cs.bilkent.edu.tr. Supplementary data are available at Bioinformatics online.

FPGA-based ultrasonic energy mapping with source removal method for damage visualization in composite structures

This paper presents the implementation of an ultrasonic energy mapping (UEM) method in a field programmable gate array (FPGA)-based processing board. This method is integrated into an ultrasonic propagation imaging (UPI) system for real-field application. UEM method involves two-dimensional Fourier transform and wavenumber filtering to capture the energy scattering waves. Performing multi-dimensional Fourier transform in FPGA is a challenging task because it cannot fit into a single FPGA chip, and therefore, external memory is required to handle a large amount of data. The row–column decomposition method is used to perform 2D Fourier transform using two DDR3 SDRAM memories. Additionally, a source removal function is added into the system to highlight the damage when high energy at the source location occurs. The UPI system was applied for inspection of a composite wing box with impact damages. The UEM results showed that a damage of 20 × 20 mm2 was detected successfully in the presence of the source inside the scan area. Moreover, the UEM result is produced in less than 5 s for 57,600 points, which is practical for a real-world, non-destructive testing application.

Mobile Robot Framework Designing and Transferring of Data by PCI Controller

&lt;p&gt;In this paper, a differential robot is designed and controlled by PCI card. This card connected between personal computer and microcontroller. Furthermore PID controller was designed by Asic device and implemented on robot.&lt;/p&gt;&lt;p&gt;In this paper, instead of using that massive hardware’s, it designed a single FPGA chip to perform the same motion control of robot wheels. We developed a general purposed motion control of robot using a field programmable gate array (FPGA).&lt;/p&gt;&lt;p&gt;In order to obtain independent robots movement, the main PID controller is implemented with a Field Programmable Gate Array. The main PID controller routine was designed to be fairly general purpose and modular form. While it is used to control a DC motor, it could be re-deployed to other situations where some parameter has to be controlled to a set value under varying conditions. The actual control software is located in a single function and its major inputs and output are held in a structure. Although it was designed originally for a specific job it is really only intended as an example of the basic techniques involved and to allow those with no control system knowledge to experiment with a simple PID system.&lt;/p&gt;&lt;p&gt;, FPGA, ATmega128L, Robot, Digital.&lt;/p&gt;

Parallel RC4 Key Searching System Based on FPGA

This paper presents an effective fieldprogrammable gate array (FPGA)-based hardware implementation of a parallel key searching system for the brute-force attack on RC4 encryption. The design employs several novel key scheduling techniques to minimize the total number of cycles for each key search and uses on-chip memories of the FPGA to maximize the number of key searching units per chip. Based on the design, a total of 176 RC4 key searching units can be implemented in a single Xilinx XC2VP20-5 FPGA chip. Operating at a 47-MHz clock rate, the design can achieve a key searching speed of 1.07 x 107 keys per second. Breaking a 40-bit RC4 encryption only requires around 28.5 h.

An Efficient FPGA based Real-Time Implementation Shunt Active Power Filter for Current Harmonic Elimination and Reactive Power Compensation

This paper proposes a new approach of Field Programmable Gate Array (FPGA) controlled digital implementation of shunt active power filter (SAPF) under steady state and dynamic operations. Typical implementations of SAPF uses microprocessor and digital signal processor (DSP) but it limited for complex algorithm structure, absence of feedback loop delays and their cost can be exceed the benefit they bring. In this paper, the hardware resources of an FPGA are configured and implemented in order to overcome conventional microcontroller or digital signal processor implementations. This proposed FPGA digital implementation scheme has very less execution time and boosts the overall performance of the system. The FPGA controller integrates the entire control algorithm of an SAPF, including synchronous reference frame transformation, phase locked loop, low pass filter and inverter current controller etc. All these required algorithms are implemented with a single all-on chip FPGA module which provides freedom to reconfigure for any other applications. The entire algorithm is coded, processed and simulated using Xilinx 12.1 ISE suite to estimate the advantages of the proposed system. The coded algorithm is also defused on a single all-on-chip Xilinx Spartan 3A DSP-XC3SD1800 laboratory prototype and experimental results thus obtained match with simulated counterparts under the dynamic state and steady state operating conditions.

Architecture of FPGA Embedded Multiprocessor Programmable Controller

This paper presents the design and implementation of a multiprocessor programmable controller in field-programmable gate array (FPGA). The novelty of the proposed solution is that it combines two approaches used so far in the domain of FPGA implementations of control algorithms, i.e., program based and hardware coded, and applies multiple processors in a single FPGA chip. The controller is programmed according to the IEC 61131-3 standard and runs control tasks in parallel. Performance tests of the prototype show that it is able to execute control programs significantly faster than industrial programmable logic controllers.