Single Event Upset Mitigation Techniques Research Articles

Improving Fault Tolerance for FPGA SoCs through Post-Radiation Design Analysis

FPGAs have been shown to operate reliably within harsh radiation environments by employing single-event upset (SEU) mitigation techniques, such as configuration scrubbing, triple-modular redundancy, error correction coding, and radiation aware implementation techniques. The effectiveness of these techniques, however, is limited when using complex system-level designs that employ complex I/O interfaces with single-point failures. In previous work, a complex SoC system running Linux applied several of these techniques only to obtain an improvement of 14 \(\times\) in mean time to failure (MTTF). A detailed post-radiation fault analysis found that the limitations in reliability were due to the DDR interface, the global clock network, and interconnect. This article applied a number of design-specific SEU mitigation techniques to address the limitations in reliability of this design. These changes include triplicating the global clock, optimizing the placement of the reduction output voters and input flip-flops, and employing a mapping technique called “striping.” The application of these techniques improved MTTF of the mitigated design by a factor of 1.54 \(\times\) and thus provides a 22.8X \(\times\) MTTF improvement over the unmitigated design. A post-radiation fault analysis using BFAT was also performed to find the remaining design vulnerabilities.

Understanding radiation effects in SRAM-based field programmable gate arrays for implementing instrumentation and control systems of nuclear power plants

Abstract Field programmable gate arrays (FPGAs) are getting more attention in safety-related and safety-critical application development of nuclear power plant instrumentation and control systems. The high logic density and advancements in architectural features make static random access memory (SRAM)-based FPGAs suitable for complex design implementations. Devices deployed in the nuclear environment face radiation particle strike that causes transient and permanent failures. The major reasons for failures are total ionization dose effects, displacement damage dose effects, and single event effects. Different from the case of space applications, soft errors are the major concern in terrestrial applications. In this article, a review of radiation effects on FPGAs is presented, especially soft errors in SRAM-based FPGAs. Single event upset (SEU) shows a high probability of error in the dependable application development in FPGAs. This survey covers the main sources of radiation and its effects on FPGAs, with emphasis on SEUs as well as on the measurement of radiation upset sensitivity and irradiation experimental results at various facilities. This article also presents a comparison between the major SEU mitigation techniques in the configuration memory and user logics of SRAM-based FPGAs.

New approach to emulate SEU faults on SRAM based FPGAS

Field Programmable Gate Arrays (FPGAs) offer high capability in implementing of complex systems, and currently are an attractive solution for space system electronics. However, FPGAs are susceptible to radiation induced Single-Event Upsets (SEUs). To insure reliable operation of FPGA based systems in a harsh radiation environment, various SEU mitigation techniques have been provided. In this paper we propose a system based on dynamic partial reconfiguration capability of the modern devices to evaluate the SEU fault effect in FPGA. The proposed approach combines the fault injection controller with the host FPGA, and therefore the hardware complexity is minimized. All of the SEU injection and evaluation requirements are performed by a soft-core which realized inside the host FPGA. Experimental results on some standard benchmark circuits reveal that the proposed system is able to speed up the fault injection campaign 50 times in compared to conventional method.

Single event upset mitigation techniques for FPGAs utilized in nuclear power plant digital instrumentation and control

Field programmable gate arrays (FPGAs) are integrated circuits being increasingly used for digital instrumentation and control (I&C) in nuclear power plants (NPPs) because of low cost, re-configurability and low design turn-around time. However, to ensure reliability, proper design techniques must be employed since the memory and logic in FPGAs are susceptible to single event upsets (SEUs). Triple modular redundancy (TMR) has become a common SEU mitigation design technique because of its straightforward implementation and reliable results. Partitioned TMR approaches are introduced in this paper, and formulae derived indicate that the maximum probability of two simultaneous errors [ P E] max is inversely proportional to the number of logic partitions in a TMR design, when each redundant logic block in every logic partition has the same number of sensitive nodes. However, the maximum logic partitioning design cannot completely eliminate the possibility of two simultaneous upsets. For the example test circuit it is found that [ P E] max is reduced dramatically from 66.67% for minimum logic partitioning to 4.44% for maximum logic partitioning. Because TMR introduces significant overhead due to its full hardware redundancy, a dual modular redundancy approach is also examined for application to less demanding situations. By comparative analysis this study reaches the conclusion that the maximum logic partitioning TMR implementation is the best solution for digital I&C applications in NPPs where obtaining robustness is of the highest importance, despite its higher area overhead.