Single-event Upset Hardness Research Articles

Single-Event Upset Tolerance Study of a Low-Voltage 13T Radiation-Hardened SRAM Bitcell

The 13T static random-access memory (SRAM) cell was designed as a low-voltage single-event upset (SEU)-tolerant device for ultralow power space applications, showing full read and write functionality down to the subthreshold voltage of 300 mV. In order to assess the SEU hardness of the device experimentally, it was tested under heavy-ion beams at the Cyclotron Resource Center, Louvain-la-Neuve, Belgium. After irradiation, bit upsets from “1” to “0” were observed, whereas bit upsets from “0” to “1” were extremely rare. Since multiple upsets occurred within addresses, we assume that in addition to random ion hits on the memory cells, the reason for the high SEU rate is ions impinging on the nonhardened peripheral circuitry. Furthermore, heavy-ion experiments and Monte Carlo simulations were performed in order to clarify the upset mechanism.

Data-Retention-Voltage-Based Analysis of Systematic Variations in SRAM SEU Hardness: A Possible Solution to Synergistic Effects of TID

Single-event upset (SEU) hardness varies across dies, wafers, and lots—even just after fabrication and further across time. Mechanisms of postfabrication variations include total ionizing dose (TID) effects, which are caused by long-term radiation exposure. This synergistic effect of TID on SEU hardness is a particular concern in integrated circuits used in space and nuclear radiation environments. This article shows that an electrical parameter called the data-retention voltage is useful in dealing with such TID effects on the SEU hardness of static random access memories (SRAMs), which are known to be particularly radiation-sensitive. Experiments showed that TID-induced variations in SRAM SEU hardness, i.e., variations in SEU cross sections, were predicted by measuring the data-retention voltage. In addition, these variations were canceled out by adjusting the power supply voltage according to its interesting relationship to the data-retention voltage. Results suggest that it might be possible in flight to predict and cancel out SEU hardness variations caused by TID and other synergistic effects.

Improved Single-Event Transient Hardness in Tunnel-Diode Body-Contact SOI nMOS

Single-event transient (SET) responses are compared for floating-body contact, T-gate body-contact (TB), and tunnel-diode body-contact (TDBC) silicon-on-insulator (SOI) MOSFETs. The influence of three body-contact schemes on SET sensitivity is examined via irradiations as functions of position, bias voltage, and device size. The mechanisms of SET in SOI devices are discussed. Although both TB and TDBC schemes suppress floating body effects (FBEs), the TDBC scheme has superior SET hardness because it effectively eliminates charge enhancement due to bipolar amplification originating from FBEs. Thus, TDBC-structure SOI devices can lead to improved single-event upset hardness in static random access memory cells.

A Soft Error Study on Tri-gate based FinFET and Junctionless-FinFET 6T SRAM Cell – A Comparison

This paper is under in-depth investigation due to suspicion of possible plagiarism on a high similarity index When junction based semiconductor devices are scaled down to extreme lower dimensions, the formation of ultra-sharp junctions between source/drain and channel becomes complex since the doping concentration has to vary by several orders of magnitudes over a distance of a few nanometers. In addition, As CMOS device is scaling down significantly, the sensitivity of Integrated Circuits (ICs) to Single Event Upset (SEU) radiation increases. As soft errors emerge as reliability threat there is a significant interest lies both at device and circuit level for SEU hardness in memories. The critical dose observed in FinFET and Junctionless-FinFET (JLT) based 6T-SRAM is given by LET = 1.4 and 0.1 pC/µm. The simulation result analyzes electrical and SEU radiation parameters of FinFET and JLT based 6T-SRAM memory circuit.

Pattern dependence in synergistic effects of total dose on single-event upset hardness**Project supported by the National Natural Science Foundation of China (Grant No. U1532261).

The pattern dependence in synergistic effects was studied in a 0.18 μm static random access memory (SRAM) circuit. Experiments were performed under two SEU test environments: 3 MeV protons and heavy ions. Measured results show different trends. In heavy ion SEU test, the degradation in the peripheral circuitry also existed because the measured SEU cross section decreased regardless of the patterns written to the SRAM array. TCAD simulation was performed. TID-induced degradation in nMOSFETs mainly induced the imprint effect in the SRAM cell, which is consistent with the measured results under the proton environment, but cannot explain the phenomena observed under heavy ion environment. A possible explanation could be the contribution from the radiation-induced GIDL in pMOSFETs.

Effect of Underlap and its Soft Error Performance in 30 nm Junctionless-based 6T-SRAM Cell

As CMOS device is scaling down significantly, the sensitivity of Integrated Circuits (ICs) to Single Event Upset (SEU) radiation increases. The Sensitivity of ICs to soft errors emerge as reliability threat which motivates significant interest in the development of various techniques both at the device and circuit level for SEU hardness in SRAM memories. To facilitate the scaling the concept of underlap Gate-Source/Drain (G-S/D) was suggested in the literature. L un is one of the sensitive geometrical parameter considered to differ from 1 nm to 5 nm in a SEU radiating environment. The effect of Gate-Source/Drain underlap (L un ) on soft error performance in 30 nm Junctionless Transistor (JLT) based on 6T-SRAM cell has been examined through extensive mixed mode-device and circuit simulations using TCAD. The critical dose observed in JLT based 6T-SRAM with L un ranging from 1 nm to 5 nm to flip the cell is given by Linear Energy Transfer (LET) between 0.05 to 0.06 pC/µm. The simulation result analyzes electrical and SEU radiation parameters to study its impact on JLT based 6T-SRAM cell.

Impact of Heavy Ion Energy and Nuclear Interactions on Single-Event Upset and Latchup in Integrated Circuits

The effects of heavy ion energy and nuclear interactions on the single-event upset (SEU) and single-event latchup (SEL) response of commercial and radiation-hardened CMOS ICs are explored. Above the threshold LET for direct ionization-induced upsets, little difference is observed in single-event upset and latchup cross sections measured using low versus high energy heavy ions. However, significant differences between low- and high-energy heavy ion test results are observed below the threshold LET for single-node direct ionization-induced upsets. The data suggest that secondary particles produced by nuclear interactions play a role in determining the SEU and SEL hardness of integrated circuits, especially at low LET. The role of nuclear interactions and implications for radiation hardness assurance and rate prediction are discussed.

Effects of Total Dose Irradiation on Single-Event Upset Hardness

The effect of total dose on SEU hardness is investigated as a function of temperature and power supply voltage to determine worst-case hardness assurance test conditions for space environments. SRAMs from six different vendors were characterized for single-event upset (SEU) hardness at proton energies from 20 to 500 MeV and at temperatures of 25 and 80degC after total dose irradiating the SRAMs with either protons, Co-60 gamma rays, or low-energy x-rays. It is shown that total dose irradiation and the memory pattern written to the memory array during total dose irradiation and SEU characterization can substantially affect SEU hardness for some SRAMs. For one SRAM, the memory pattern made more than two orders of magnitude difference in SEU cross section at the highest total dose level examined. For all SRAMs investigated, the memory pattern that led to the largest increase in SEU cross section was the same memory pattern that led to the maximum increase in total-dose induced power supply leakage current. In addition, it is shown that increasing the temperature during SEU characterization can also increase the effect of total dose on SEU hardness. As a result, worst-case SEU hardness assurance test conditions are the maximum total dose and temperature of the system environment, and the minimum operating voltage of the SRAM. Possible screens for determining whether or not the SEU cross section of an SRAM will vary with total dose, based on the magnitude of the increase in power supply leakage current with total dose or the variation in SEU cross section with power supply voltage, have been suggested. In contrast to previous works, our results using selective area x-ray irradiations show that the source of the effect of total dose on SEU hardness is radiation-induced leakage currents in the memory cells. The increase in SEU cross section with total dose appears to be consistent with radiation-induced currents originating in the memory cells affecting the output bias levels of bias level shift circuitry used to control the voltage levels to the memory cells and/or due to the lowering of the noise margin of individual memory cells caused by radiation-induced leakage currents

Radiation effects in SOI technologies

Silicon-on-insulator (SOI) technologies have been developed for radiation-hardened applications for many years and are rapidly becoming a main-stream commercial technology. The authors review the total dose, single-event effects, and dose rate hardness of SOI devices. The total dose response of SOI devices is more complex than for bulk-silicon devices due to the buried oxide. Radiation-induced trapped charge in the buried oxide can increase the leakage current of partially depleted transistors and decrease the threshold voltage and increase the leakage current of fully depleted transistors. Process techniques that reduce the net amount of radiation-induced positive charge trapped in the buried oxide and device design techniques that mitigate the effects of trapped charge in the buried oxide have been developed to harden SOI devices to bulk-silicon device levels. The sensitive volume for charge collection in SOI technologies is much smaller than for bulk-silicon devices potentially making SOI devices much harder to single-event upset (SEU). However, bipolar amplification caused by floating body effects can significantly reduce the SEU hardness of SOI devices. Body ties are used to reduce floating body effects and improve SEU hardness. SOI ICs are completely immune to classic four-layer p-n-p-n single-event latchup; however, floating body effects make SOI ICs susceptible to single-event snapback (single transistor latch). The sensitive volume for dose rate effects is typically two orders of magnitude lower for SOI devices than for bulk-silicon devices. By using body ties to reduce bipolar amplification, much higher dose rate upset levels can be achieved for SOI devices than for bulk-silicon devices.

A methodology for identifying laser parameters for equivalent heavy-ion hits

Pulsed lasers show excellent promise for single-event upset (SEU) studies in laboratory environments due to their simplicity of use. However, a one-to-one relationship between a laser hit and a heavy-ion hit has not been developed so far. With the assumption that the collected charge from a SEU hit dictates the circuit-level response, equivalency between a laser hit and heavy-ion hit can be established if the collected charge from both hits is identical. This paper presents a methodology to identify the equivalent laser characteristics for a heavy-ion hit by calculating the collected charge through device-level simulations. Such knowledge will enable SEU hardness assurance of circuits using lasers.

SEU-hardened silicon bipolar and GaAs MESFET SRAM cells using local redundancy techniques

Silicon bipolar and GaAs FET SRAMs have proven to be more difficult to harden with respect to single-event upset (SEU) mechanisms than have silicon CMOS SRAMs. This is a fundamental property of bipolar and JFET or MESFET device technologies which do not have a high-impedance, nonactive isolation between the control electrode and the current of voltage being controlled. All SEU circuit-level hardening techniques applied at the local cell level must use some type of information storage redundancy so that information loss on one node due to an SEU event can be recovered from information stored elsewhere in the cell. Several approaches to the use of local redundancy in bipolar and FET technologies are discussed. At the expense of increased cell complexity and increased power consumption and write time, several approaches are capable of providing complete SEU hardness at the local cell level.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Scaling of Gamma Dose Rate Upset Threshold in High Density Memories

Pulsed gamma upset threshold for high density RAMs is explored using constant field scaling rules. The analysis indicates that the upset threshold for DRAMs will not decrease with increased levels of integration and may improve relative to present technology. Potential improvement may be limited by statistical effects in gamma energy deposition. It is shown that statistical effects are magnified both by the increasing number of memory cells on a chip and by their extremely small feature size. Extreme value statistical techniques are used to determine worst-case cell memory loss. The paper also presents parallels of pulsed gamma and single event upset (SEU) effects that may be useful in SEU hardness assurance for VLSI memories.