Single Event Radiation Effects Research Articles

FAINTSTAR: an intelligent single-chip sensor head for star trackers—prototype results

Since 2003 the European Space Agency’s roadmap for star tracker CMOS APS (active pixel) image sensors has included developments to integrate significant logic functionality with the pixel array, aiming at an imaging system-on-chip. FaintStar (FS) will be the first commercially available product resulting from these activities. FaintStar is being developed by ams Sensors Belgium (formerly CMOSIS) in two phases. Phase 1 served to specify, design, manufacture, and characterise a prototype chip, informally named FaintStar1 (FS1), the subject of this paper. FaintStar is a one megapixel image sensor with 10 µm pixels and rolling shutter. All interactions with the user are over a single 80 Mb/s SpaceWire link. FaintStar offers various readout modes (full frame, windowed, windowed with dual rolling shutter, etc.). The chip has ‘pixels-to-centroids’ processing, including transfer curve linearisation, bad pixel replacement, background image estimation and suppression, spike filtering, bright object extraction, and photometric barycentre calculation. The algorithms used are generic, i.e., non-reliant on third-party IP, yet highly user-configurable. Data-compressed or raw image output is also supported. The device has been developed for star trackers mainly, although applications such as high-accuracy sun sensing, and navigation, rendezvous, or rover cameras are also served. The prototype chip exceeds its expectations. This article starts with an overview of the FS1 design and reports on the Phase 1 characterisation results, including electro-optical performance, proton displacement damage, total dose, and single event radiation effects. Started end of 2017, the project’s Phase 2 entails minor design refinements, creating FaintStar2 (FS2), its manufacturing, and then a formal evaluation campaign. After this, the sensor will be offered as a commercial off-the-shelf product.

Error Resilient GPU Accelerated Image Processing for Space Applications

Significant advances in spaceborne imaging payloads have resulted in new big data problems in the Earth Observation (EO) field. These challenges are compounded onboard satellites due to a lack of equivalent advancement in onboard data processing and downlink technologies. We have previously proposed a new GPU accelerated onboard data processing architecture and developed parallelised image processing software to demonstrate the achievable data processing throughput and compression performance. However, the environmental characteristics are distinctly different to those on Earth, such as available power and the probability of adverse single event radiation effects. In this paper, we analyse new performance results for a low power embedded GPU platform, investigate the error resilience of our GPU image processing application and offer two new error resilient versions of the application. We utilise software based error injection testing to evaluate data corruption and functional interrupts. These results inform the new error resilient methods that also leverages GPU characteristics to minimise time and memory overheads. The key results show that our targeted redundancy techniques reduce the data corruption from a probability of up to 46 percent to now less than 2 percent for all test cases, with a typical execution time overhead of 130 percent.

Tolerance of the High Energy X-ray Imaging Technology ASIC to potentially destructive radiation processes in Earth-orbit-equivalent environments

The High Energy X-ray Imaging Technology (HEXITEC) ASIC is designed on a 0.35 μm CMOS process to read out CdTe or CZT detectors and hence provide fine-pixellated spectroscopic imaging in the range 2–200 keV. In this paper, we examine the tolerance of HEXITEC to both potentially destructive cumulative and single event radiation effects. Bare ASICs are irradiated with X-rays up to a total ionising dose (TID) of 1 Mrad (SiO2) and bombarded with heavy ions with linear energy transfer (LET) up to 88.3 MeV mg−1 cm−2. HEXITEC is shown to operate reliably below a TID of 150 krad, have immunity to fatal single event latchup (SEL) and have high tolerance to non-fatal SEL up to LETs of at least 88.3 MeV mg−1 cm−2. The results are compared to predictions of TID and SELs for various Earth-orbits and aluminium shielding thicknesses. It is found that HEXITEC's radiation tolerance to both potentially destructive cumulative and single event effects is sufficient to reliably operate in these environments with moderate shielding.

Single-Event Multiple-Transient Characterization and Mitigation via Alternative Standard Cell Placement Methods

As fabrication technology scales towards smaller transistor sizes and lower critical charge, single-event radiation effects are more likely to cause errant behavior in multiple, physically adjacent devices in modern integrated circuits (ICs), and with higher operating frequencies, this risk increasingly impacts design logic over memory as well. In order to increase future system reliability, circuit designers need greater awareness of multiple-transient charge-sharing effects during the early stages of their design flow with standard cell placement and routing. To measure the propagation and observability of multiple transients from single radiation events, this work uses several intra-pipeline combinational logic circuits at the 32nm technology node, investigates several different standard cell placements of each design, and analyzes those placements with a novel, physically realistic transient injection and simulation method. It is shown that (1) this simulation methodology, informed by experimental data, provides an increased realism over other works in traditional fault injection fields, (2) different placements of the same circuit where standard cells are grouped by logical hierarchy can result in different reliability behavior and benefits especially useful within the area of approximate computing, and (3) improved reliability through charge-sharing transient mitigation can be gained with no area penalty and minimal speed and power penalties by adjusting the placement of standard cells.

Predictions of integrated circuit serviceability in space radiation fields

The present paper suggests an approach to estimating and predicting the serviceability of on-board electronic equipment. It is based on the postulates of the reliability theory and accounts for total-dose and single-event radiation effects as well as other exterior destabilizing factors. The methods of determination of failure and upset rates for CMOS devices are considered. The probability of non-failure operation of a two CMOS RAM is calculated along the whole trajectory of the “Solar Probe” spacecraft.

Cosmic and terrestrial single-event radiation effects in dynamic random access memories

A review of the literature on single-event radiation effects (SEE) on MOS integrated-circuit dynamic random access memories (DRAMs) is presented. The sources of single-event (SE) radiation particles, causes of circuit information loss, experimental observations of SE information upset, technological developments for error mitigation, and relationships of developmental trends to SE vulnerability are discussed.