Single Event Latchup Protection Research Articles

Circuit-Level Simulation of the Single Event Transients in an On-Chip Single Event Latchup Protection Switch

The circuit-level simulation analysis of the single event transient response of an on-chip single event latchup protection switch (SPS cell), previously designed and developed in the IHP 250 nm CMO...

Fault-tolerant TMR and DMR circuits with latchup protection switches

The paper presents CMOS ASICs which can tolerate the single event upsets (SEUs), the single event transients (SET), and the single event latchup (SEL). Triple and double modular redundant (TMR and DMR) circuits in combination with SEL protection switches (SPS) make the base of the proposed approach. The SPS had been designed, characterized, and verified before it became a standard library cell. A few additional steps during logic synthesis and layout generation have been introduced in order to implement the redundant net-lists and power domains as well as to place the latchup protection switches. The approach and accompanying techniques have been verified on the example of a shift-register and a middleware switch processor.

A New Analyzing Method of Single Event Latch-Up Protection Circuit Based on Current Comparing and Its Performance Verification

Single event latch-up (SEL) is a significant issue for electronics design in space application, which would cause large currents in electronic devices, and may lead to burning out of devices. A new monitoring circuit based on current-comparing method is designed to protect the electronics away from SEL’s damage in radiation environment. The response time of protection circuit has been analyzed. The signal simulation results indicated that the operating time of the SEL protection circuit is dependent on the action time of current comparator and system application recovery time. The function of the monitoring circuit protection device away from SEL’s damage has validated through experiment at last.