Single Ended Research Articles

Novel Low-Power Computing-In-Memory (CIM) Design for Binary and Ternary Deep Neural Networks by Using 8T XNOR SRAM

The increasing demand for high-performance and low-power hardware in artificial intelligence (AI) applications, such as speech recognition, facial recognition, and object detection, has driven the exploration of advanced memory designs. Convolutional neural networks (CNNs) and deep neural networks (DNNs) require intensive computational resources, leading to memory access times and power consumption challenges. To address these challenges, we propose the application of computing-in-memory (CIM) within FinFET-based 8T SRAM structures, specifically utilizing P-latch N-access (PLNA) and single-ended (SE) configurations. Our design significantly reduces power consumption by up to 56% in the PLNA configuration and 60% in the SEconfiguration compared to traditional FinFET SRAM designs. These reductions are achieved while maintaining competitive delay performance, making our approach a promising solution for implementing efficient and low-power AI hardware. Detailed simulations in 7 nm FinFET technology underscore the potential of these CIM-based SRAM structures in overcoming the computational bottlenecks associated with DNNs and CNNs.

Photovoltaic MPPT Control Using Sepic Converter Based on Super Twisting Control

Abstract For ensuring a greener and low carbon future; renewable energies sources such as solar energy stands out as a prominent solution for generating sustainable and clean electricity due to its accessibility, abundance and numerous benefits. The use of solar panel also called as photovoltaic systems has more importance in the world for their ability to convert sun irradiation into electricity while they have significant drawbacks like the nonlinearity of Pv panel. The efficiency and performance of Photovoltaic (PV) systems can be influnced by various factors, like climate fluctuations during the day. Therefore, it is so important to optimize the power capturing from PV panels. To optimize the energy created by photovoltaic modules, it is necessary to carefully select a DC-DC converter with MPPT control. This guarantees that the maximum power is extracted from the solar power plant and sent to the demand side in less time and with greater effectiveness. This paper introduces a super twisting sliding mode control technique for achieving maximum power point tracking (MPPT) in a photovoltaic (PV) system. The Single Ended Primary Inductor Converter (SEPIC) is proposed as a superior alternative to the conventional boost dc-dc converter, as it enables the extraction of the highest possible power from the photovoltaic panels array. Upon doing a thorough comparison of the suggested control with the P&O algorithm in various scenarios using the MATLAB/SIMULINK tool, it was found that the provided STC (Synchronous Tracking Control) for the SEPIC converter demonstrates greater efficiency and reduced oscillation around the Maximum Power Point (MPP).

DEVELOPMENT OF DUAL-SWITCHES BRIDGELESS PFC TOTEM-POLE SEPIC CONVERTER FOR LED DRIVER APPLICATION

This paper presents a Dual-Switch Bridgeless Power Factor Correction (DSBPFC) Single Ended Primary Inductor Converter (SEPIC) with Totem-Pole circuit structure for LED Driver Application. The conventional Full-Bridge Rectifier (FBR) SEPIC converter has five diodes, four in the rectifier bridge and one in the SEPIC. In addition, the FBR SEPIC converter has several drawbacks, including low power factor (PF), high current harmonics (THDi), and high output voltage ripple, due to the combination of two operation circuits in a single converter structure. The proposed DSBPFC SEPIC converter with Totem-Pole method improves PF and reduces THDi and output voltage ripple compared to the conventional FBR SEPIC. Additionally, it only requires three diodes instead of five. The optimization parameter design minimizes the THDi and output voltage ripple. In addition, to improve the quality of the AC source, the inductors are designed to operate in DCM and CCM based on the ripple-balancing concept between input and output inductors. As to reduce output voltage ripple, a high capacitance of output capacitor is used. The simulation result of the THDi is 3.8% whereas the experimental result shows that the THDi is 23.5%; which can be attributed to the parasitic elements at the passive components. Furthermore, the experimental results of the output voltage ripple are 2 V with output capacitance of 3300 μF, compared to the output voltage ripple of 4.40 V for 470 μF. Therefore, the proposed converter's design is confirmed with an output power of approximately 14.4 W.

The Behaviours of Various DC Choppers during Shading Occurrence in PV Systems

This paper investigates how the DC choppers behave during the shading occurrence at different time intervals of the year. Three types of DC choppers are implemented during the same shading conditions and intervals of time. The studied parameters are the duty cycle, output power, current, and switch losses. The mathematical model is built and implemented using the MATLAB/Simulink platform. The obtained results show that the SEPIC converter has the highest rate of duty cycle, which means more switching losses are generated. Concerning the average output power, the Modified Single Ended Primary Converter (MSEPIC) has the highest rate, while the Boost Converter has the lowest rate. The MPP power, duty cycle, and switching losses are studied under various shading rates. The duty cycle has the highest rate on the SEPIC converter, while MSEPIC has the lowest rate. Despite that, the switching losses are tremendously high at MSEPIC compared to SEPIC converters. Furthermore, simulation studies show that Boost and SEPIC converters have better performance in frequent cloudy weather conditions.

Enhancing MPPT performance for partially shaded photovoltaic arrays through backstepping control with Genetic Algorithm-optimized gains

As the significance and complexity of solar panel performance, particularly at their maximum power point (MPP), continue to grow, there is a demand for improved monitoring systems. The presence of variable weather conditions in Maroua, including potential partial shadowing caused by cloud cover or urban buildings, poses challenges to the efficiency of solar systems. This study introduces a new approach to tracking the Global Maximum Power Point (GMPP) in photovoltaic systems within the context of solar research conducted in Cameroon. The system utilizes Genetic Algorithm (GA) and Backstepping Controller (BSC) methodologies. The Backstepping Controller (BSC) dynamically adjusts the duty cycle of the Single Ended Primary Inductor Converter (SEPIC) to align with the reference voltage of the Genetic Algorithm (GA) in Maroua’s dynamic environment. This environment, characterized by intermittent sunlight and the impact of local factors and urban shadowing, affects the production of energy. The Genetic Algorithm is employed to enhance the efficiency of BSC gains in Maroua’s solar environment. This optimization technique expedites the tracking process and minimizes oscillations in the GMPP. The adaptability of the learning algorithm to specific conditions improves energy generation, even in the challenging environment of Maroua. This study introduces a novel approach to enhance the efficiency of photovoltaic systems in Maroua, Cameroon, by tailoring them to the specific solar dynamics of the region. In terms of performance, our approach surpasses the INC-BSC, P&O-BSC, GA-BSC, and PSO-BSC methodologies. In practice, the stabilization period following shadowing typically requires fewer than three iterations. Additionally, our Maximum Power Point Tracking (MPPT) technology is based on the Global Maximum Power Point (GMPP) methodology, contrasting with alternative technologies that prioritize the Local Maximum Power Point (LMPP). This differentiation is particularly relevant in areas with partial shading, such as Maroua, where the use of LMPP-based technologies can result in power losses. The proposed method demonstrates significant performance by achieving a minimum 33% reduction in power losses.

A 10-bit 33.3-kS/s 3.2-fJ/conversion-step single-ended counter-type SAR ADC with dual 5-bit CDAC arrays and counters in 65-nm CMOS

In this paper, an area-and-energy-efficient 10-bit single-ended (SE) counter-type (CT) analog-to-digital converter (ADC) with dual 5-bit capacitive digital-to-analog converter (DAC) arrays and dual 5-bit counters is presented. The 10-bit capacitive-DAC (CDAC) array and counter of the conventional counter-type structure are divided into two 5-bit CDAC arrays and counters, respectively. Significant improvements are achieved in comparison to the conventional counter-type ADC as follows: the capacitance of the most-significant-bit (MSB) capacitor is reduced by 96.88 % from 512C to 16C; the total capacitors are reduced by 93.75 % from 1024C to 64C; the total clock cycles required in the conversion phase are reduced by 93.94 % from 1023 to 62; the average switching energy is reduced by 98.55 % from 2390CV2 to 35CV2. The proposed ADC occupies a smaller area, performs much faster, and its power consumption is greatly reduced. This structure has a simple design with small sampling capacitor (32C) and does not require a rail-to-rail comparator compared to SAR ADCs. It is suitable for biomedical and multi-channel applications. The proposed ADC is post-layout simulated in 65-nm CMOS technology which occupies 0.016 mm2 area. This ADC has 85.43 nW power consumption, 9.64 ENOB on 33.33 kS/s sampling rate, and 3.23 fJ/conversion-step FOM.

PID-Based control of sepic power stage with QS bacterial-based search algorithm for renewable energy applications

In response to the growing need for efficient power conversion in renewable energy applications, this study addresses the issue of harmonic distortion and low Power Factor (PF) values caused by non-linear loads, such as electronic devices. Low PF results in reduced efficiency, increased energy consumption, and higher costs for both consumers and utilities. Active correction, typically involving an active circuit implemented using a power converter, provides an optimal solution by offering high performance, precise regulation, and low harmonic distortion. This research proposes a Power Factor Correction (PFC) solution utilizing an Interleaved DC-DC Single Ended Primary Inductance Converter (SEPIC) for the power stage and a Proportional Integral Derivative (PID) controller for the control block, tuned by a Quorum Sensing (QS) bacterial-based search algorithm. The PID controller parameters are derived using a frequency-domain approach, which presents advantages such as reduced design complexity, improved stability margins, and enhanced SEPIC performance. Simulation results indicate reduced overshoot, settling time, rise time, and Total Harmonic Distortion (THD) percentage, as well as increased efficiency and power factor nearing unity. The proposed scheme also demonstrates improved dynamic performance for variations in load, line, and reference voltage. Owing to its high efficiency, precise voltage regulation, and minimized impact on the electrical grid, this solution is well-suited for renewable energy applications, where optimizing energy conversion and ensuring stable operation are crucial for the overall performance of renewable energy systems.

A 15-Gb/s Single-Ended NRZ Receiver Using Self-Referenced Technique With 1-Tap Latched DFE for DRAM Interfaces

This brief presents a single-ended (SE) receiver (RX) with a self-referenced (SR) technique using sample and hold (S&H) circuits. The proposed RX does not require a reference voltage (VREF) for data recovery by comparing the present data with previous data. The RX was implemented as half-rate architecture to halve the clock frequency and facilitate the S&H operation. Moreover, the proposed decision feedback equalizer (DFE) is suitable for SR RX and improves the reliability of RX by eliminating inter-symbol interference (ISI). The prototype RX, fabricated using 28-nm CMOS technology, occupies a 0.0016 mm2 active area. The measurement result of the proposed RX achieves a bit-error-rate (BER) under 10−12 with a 15-Gb/s data rate in a 17-inch PCB FR4 channel. The RX consumes 13.56 mW of power and has a power efficiency of 0.90 pJ/bit.

Analysis of Various Topologies and Control Circuit used in Single Phase EV Charger

Abstract: In remote electric vehicle charging frameworks utilizing inductive power transfer (IPT), power electronic converters assume a basic part in decreasing size and cost, as well as boosting the proficiency of the whole framework. As of late, analysts have led huge examination studies to work on the exhibition of power transformation frameworks, including power converter topologies and control plans. Incorporated On-Board Battery Chargers (OBC) have been acquainted as ideal arrangement with increase of electric vehicle (EV) market penetration and limit the general expense of EVs. OBCs are by and large arranged into triphasic and monophasic types with unidirectional or bidirectional power stream. Existing electric vehicle (EV) chargers utilize a hard-core non-linear diode bridge-rectifier (BR) to exploit the DC volt at the contribution of the DC converter and acquaint quality of the power is a counted as a problem with the AC input. These problems insist improvement in Power Quality for existing battery charger for this purpose the bridgeless Cuk Converter is used with the flyback converter. Cuk Converter used single diode and switch and provide additional advantage like reduction in the switch volt-stress and higher efficiency equated to the other conventional bridgeless (BL) converters. Similarly, bridgeless isolated Zeta-Luo converter with PF correction is also used. The Zeta and Luo is functioned for the half cycle of the supply individually and give the benefits of the both topologies. In this paper BL Zeta, BL Cuk, BL Buck-Boost, BL Luo, BL Single Ended Primary Inductance Converter (BL SPIC), and Canonical Switched Cell (CSC) converters are reviewed.

A Soft Switched Single Ended Primary Inductor Converter Power Factor Correction Circuit for Low Power Applications

Wydawnictwo SIGMA-NOT wydaje czasopisma fachowe informujące swoich czytelników o najnowszych osiągnięciach naukowych i nowoczesnych rozwiązaniach technicznych w Polsce i na świecie, popularyzuje problemy techniczne oraz poszerza wiedzę i kulturę techniczną.

Compact CMOS Wideband Instrumentation Amplifiers for Multi-Frequency Bioimpedance Measurement: A Design Procedure

The design of an instrumentation amplifier (IA), based on indirect current feedback and suited to electrical bioimpedance spectroscopy, is presented. The IA consists of two transconductors and a summing stage, featuring a single-stage configuration process that allows the maximum achievable bandwidth to be extended. The transconductors are linearized by means of resistive source degeneration, whereas the use of super source followers allows a reduction in the values of the source degeneration resistors. This fact leads to a decrease in the overall noise and the silicon area, thus resulting in a compact implementation. A thorough analysis of the proposed solution, accompanied by a design procedure and verified by means of electrical simulations, is also provided. Two versions of the IA, i.e., a single-ended (SE) and a pseudo-differential (PD) structure, were designed and fabricated using 180 nm CMOS technology to operate with a 1.8 V supply. The experimental results, including a BW of 5.2 MHz/8.0 MHz, a CMRR higher than 72 dB/80 dB, a DC current consumption of 139.0 μA/219.3 μA and a silicon area equal to 0.0173 mm2/0.0291 mm2 for the SE/PD implementation, validate the suitability of the approach.

A High CMRR Instrumentation Amplifier Employing Pseudo-Differential Inverter for Neural Signal Sensing

The next generation of the wearable and implantable high-density neural signal sensing systems must be multi-channel and power efficient. The integrated instrumentation amplifier (IA) within such sensing system forms the critical element for signal detection and pre-processing. Inverter-based IA provides a low power consumption and a small die area. However, the conventional inverter yields a single-ended (SE) topology, which suffers from a poor common-mode rejection ratio (CMRR). In this paper, a pseudo-differential inverter is proposed. It provides an alternative solution to increase CMRR without the need for external control circuit. The pseudo input terminal is simply employed by equally splitting the input transistor of SE inverter into two and connected in parallel (reuses the active load), to provide a feedback path to dynamically reduce the common-mode interference. With respect to the SE topology, CMRR is much improved (approximately 75% higher) without any significant increasing of die area and power consumption. The proposed IA provides circa 117 dB CMRR, 1.5 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{G}\pmb \Omega $ </tex-math></inline-formula> input impedance at 100 Hz, and consumes <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$8.3~\pmb \mu \text{W}$ </tex-math></inline-formula> .

Efficient Supply Current Control Strategies for Bridgeless Interleaved AC-DC Converter

This paper presents an efficient supply current wave shaping technique for bridgeless interleaved Single Ended Primary Inductor Converter (SEPIC). The SEPIC converter converts an Alternating Current (AC) to Direct Current (DC) with the boost converter. Power Factor Correction (PFC) is progressively significant to achieve high energy efficiency. The overall system efficiency can be increased as the bridgeless topology has less conduction losses from rectifying bridges. Also, the bridgeless and interleaved techniques are incorporated in this study to achieve better performance. The performance of the system is analyzed on both current control and sensor-less techniques. Different controllers such as Proportional Integral (PI) control, peak current control, Non-Linear Carrier (NLC) control, and sensor-less current control are integrated. All the above controllers are implemented using MATrix LABoratory (MATLAB)/SIMULINK. The performance parameter, namely Power Factor (PF), Total Harmonic Distortion (THD), is computed for both open loop and closed loop condition. The sensor-less current control method is implemented using the DsPIC30F2010 controller. The circuit performance is also verified from the simulation and hardware results. The proposed controller has inbuilt Analog-to-Digital Converter (ADC), Digital-to-Analog Converter (DAC), Pulse Width Modulation (PWM) generator, and provides fast responses.

Magnetless microstrip circulators based on differential spatiotemporal modulation of resonators

This article presents a magnetless differential microstrip circulator for high frequency operation. The differential design is obtained by pairing two single-ended (SE) circulators, each based on three resonators connected in a wye topology with spatiotemporal modulation (STM). What is more, the STM biases of the two SE circulators are kept a fixed 180° phase difference. The resonance of the circuit is realized by varactor-loaded microstrip line sections rather than conventional series of inductor and varactor. The design method of the proposed microstrip circulator has been presented by analyzing its equivalent circuit, which indicates the microstrip line sections cannot be simply equivalent to inductors with the conventional method. The analysis of the time-varying circuit is verified by the simulated results of both the microstrip circulator and its equivalent circuit. A magnetless microstrip circulator was designed, fabricated and measured at center frequency of 1.99 GHz, showing maximum isolation (IX) of more than 50 dB, minimum insertion loss of 4.8 dB, and 1.4% 20 dB IX bandwidth.

SAFIR-I: Design and Performance of a High-Rate Preclinical PET Insert for MRI.

(1) Background: Small Animal Fast Insert for MRI detector I (SAFIR-I) is a preclinical Positron Emission Tomography (PET) insert for the Bruker BioSpec 70/30 Ultra Shield Refrigerated (USR) preclinical 7 Magnetic Resonance Imaging (MRI) system. It is designed explicitly for high-rate kinetic studies in mice and rats with injected activities reaching 500 , enabling truly simultaneous quantitative PET and Magnetic Resonance (MR) imaging with time frames of a few seconds in length. (2) Methods: SAFIR-I has an axial field of view of and an inner diameter of 114 . It employs Lutetium Yttrium OxyorthoSilicate (LYSO) crystals and Multi Pixel Photon Counter (MPPC) arrays. The Position-Energy-Timing Application Specific Integrated Circuit, version 6, Single Ended (PETA6SE) digitizes the MPPC signals and provides time stamps and energy information. (3) Results: SAFIR-I is MR-compatible. The system’s Coincidence Resolving Time (CRT) and energy resolution are between and Full Width at Half Maximum (FWHM) at low activity and and FWHM at 550 , respectively. The peak sensitivity is ∼. The excellent performance facilitated the successful execution of first in vivo rat studies beyond 300 . Based on features visible in the acquired images, we estimate the spatial resolution to be ∼2 in the center of the Field Of View (FOV). (4) Conclusion: The SAFIR-I PET insert provides excellent performance, permitting simultaneous in vivo small animal PET/MR image acquisitions with time frames of a few seconds in length at activities of up to 500 .

Sensorless Control of Voltage Peaks in Class-E Single-Ended Resonant Inverter for Induction Heating Rice Cooker

Single-ended (SE) resonant inverters are widely used as power converters for high-pressure rice cooker induction, with 1200 V insulated-gate bipolar transistors (IGBTs) being used as switching devices for kW-class products. When voltage fluctuations occur at the input stage of an SE resonant inverter, the resonant voltage applied to the IGBT can be directly affected, potentially exceeding the breakdown voltage of the IGBT, resulting in its failure. Consequently, the resonant voltage should be limited to below a safety threshold—hardware resonant voltage limiting methods are generally used to do so. This paper proposes a sensorless resonant voltage control method that limits the increase in the resonant voltage caused by overvoltage or supply voltage fluctuations. By calculating and predicting the resonance voltage through the analysis of the resonance circuit, the resonance voltage is controlled not to exceed the breakdown voltage of the IGBT. The experimental results of a 1.35 kW SE resonant inverter for a high-pressure induction heating rice cooker were used to verify the validity of the proposed sensorless resonant voltage limiting method.

Multiple Use SiPM Integrated Circuit (MUSIC) for Large Area and High Performance Sensors

The 8-channel Multiple Use Silicon Photo-multiplier (SiPM) Integrated Circuit (MUSIC) Application specific integrated circuit (ASIC) for SiPM anode readout has been designed for applications where large photo-detection areas are required. MUSIC offers three main features: (1) Sum of the eight input channels using a differential output driver, (2) eight individual single ended (SE) analog outputs, and (3) eight individual SE binary outputs using a time over threshold technique. Each functionality, summation and individual readout includes a selectable dual-gain configuration. Moreover, the signal sum implements a dual-gain output providing a 15-bit dynamic range. The circuit contains a tunable pole zero cancellation of the SiPM recovery time constant to deal with most of the available SiPM devices in the market. Experimental tests show how MUSIC can linearly sum signals from different SiPMs and distinguish even a few photons. Additionally, it provides a single photon output pulse width at half maximum (FWHM) between 5–10 ns for the analog output and a single-photon time resolution (SPTR) around 118 ps sigma using a Hamamatsu SiPM S13360-3075CS for the binary output. Lastly, the summation mode has a power consumption of ≈200 mW, whereas the individual readout consumes ≈30 mW/ch.

Ultra-Low Power and High-Throughput SRAM Design to Enhance AI Computing Ability in Autonomous Vehicles

Power consumption and data processing speed of integrated circuits (ICs) is an increasing concern in many emerging Artificial Intelligence (AI) applications, such as autonomous vehicles and Internet of Things (IoT). Existing state-of-the-art SRAM architectures for AI computing are highly accurate and can provide high throughput. However, these SRAMs have problems that they consume high power and occupy a large area to accommodate complex AI models. A carbon nanotube field-effect transistors (CNFET) device has been reported as a potential candidates for AI devices requiring ultra-low power and high-throughput due to their satisfactory carrier mobility and symmetrical, good subthreshold electrical performance. Based on the CNFET and FinFET device’s electrical performance, we propose novel ultra-low power and high-throughput 8T SRAMs to circumvent the power and the throughput issues in Artificial Intelligent (AI) computation for autonomous vehicles. We propose two types of novel 8T SRAMs, P-Latch N-Access (PLNA) 8T SRAM structure and single-ended (SE) 8T SRAM structure, and compare the performance with existing state-of-the-art 8T SRAM architectures in terms of power consumption and speed. In the SRAM circuits of the FinFET and CNFET, higher tube and fin numbers lead to higher operating speed. However, the large number of tubes and fins can lead to larger area and more power consumption. Therefore, we optimize the area by reducing the number of tubes and fins without compromising the memory circuit speed and power. Most importantly, the decoupled reading and writing of our new SRAMs cell offers better low-power operation due to the stacking of device in the reading part, as well as achieving better readability and writability, while offering read Static Noise Margin (SNM) free because of isolated reading path, writing path, and greater pull up ratio. In addition, the proposed 8T SRAMs show even better performance in delay and power when we combine them with the collaborated voltage sense amplifier and independent read component. The proposed PLNA 8T SRAM can save 96%, while the proposed SE 8T SRAM saves around 99% in writing power consumption compared with the existing state-of-the-art 8T SRAM in FinFET model, as well as 99% for writing operation in CNFET model.

Reflected Traveling Wave Based Single-Ended Fault Location in Distribution Networks

Traveling wave (TW)-based fault-location methods have been used to determine single-phase-to-ground fault distance in power-distribution networks. The previous approaches detected the arrival time of the initial traveling wave via single ended or multi-terminal measurements. Regarding the multi-branch effect, this paper utilized the reflected waves to obtain multiple arriving times through single ended measurement. Potential fault sections were estimated by searching for the possible traveling wave propagation paths in accordance with the structure of the distribution network. This approach used the entire propagation of a traveling wave measured at a single end without any prerequisite of synchronization, which is a must in multi-terminal measurements. The uniqueness of the fault section was guaranteed by several independent single-ended measurements. Traveling waves obtained in a real 10 kV distribution network were used to determine the fault section, and the results demonstrate the significant effectiveness of the proposed method.

Variable Structure Controller for Chaos Elimination in a Single Ended Primary Inductance Converter

The paper attempts to off-set the circuit parasitics and the inherent switching nature of the power switch in a SEPIC (Single Ended Primary Inductance Converter) that eclipses its performance from theoretical predictions. The focus orients to design a control strategy that offers a chaotic free operation of the SEPIC. It envisages the use of a Variable Structure Control (VSC) strategy to irradiate the adverse effects of non-linear dynamics and assuage the operating range of the converter. The scheme projects the creation and elimination of this nonlinear property through time domain waveforms and phase portraits. The methodology underscores the theory to ensure an uniform rate of charging and discharging for the inductor current during the process of the converter operating the load. The scheme realizes the benefits of the mechanism through a correlation between the open and closed loop inductor current time domain waveform, with the help of adjustments in the parametric variations. The effort involves evaluating the performance using MATLAB simulation and experimental validation in a DSPIC (Digital signal peripheral interface controller) environment to illustrate its suitability for practical applications.