Single-electron Tunneling Transistors Research Articles

3etunneling processes in a superconducting single-electron tunneling transistor

A current due to a tunneling event that involves three times the charge of an electron was observed in the current - voltage characteristics of a superconducting single-electron tunneling transistor. In this tunnel event, a Cooper pair tunnels through one tunnel barrier simultaneously with a quasiparticle that tunnels through a second tunnel barrier which is about 0.5 microns distant from the first tunnel barrier. This current was observed in a bias regime where current flow due to sequential quasiparticle tunneling is forbidden due to the Coulomb blockade.

Coulomb blockade effects at room temperature in thin-film nanoconstrictions fabricated by a novel technique

A technique was developed to fabricate and probe nanosize tunneling structures in thin metallic films. Using oblique evaporation through conventional undercut electron-beam lithographic masks, as the sample resistance was measured in situ, we defined constrictions with widths and lengths of about 10 nm in thin granular palladium films. The tunneling conductivity through a network of metallic grains was studied. Single electron tunneling transistor effects were registered. An electrostatic gate voltage at room temperature could clearly modulate Coulomb blockade offsets of the order of 0.1 V in the current–voltage curves.

Direct patterning of single electron tunneling transistors by high resolution electron beam lithography on highly doped molecular beam epitaxy grown silicon films

We present a fabrication method for a single electron tunneling transistor (SETT) in silicon. The process is based on bonded and etched back silicon on insulator material with a 40 nm thick highly n-doped Si layer grown by molecular beam epitaxy. The nanometer structure of the SETT is defined by electron beam lithography in combination with a two-layer resist system. The pattern is transferred by anisotropic reactive ion etching. The devices are passivated by low temperature remote plasma enhanced chemical vapor deposition of high quality silicondioxide. An extended region of low conductivity is observed even at T=130 K in the current–voltage characteristics, outside of which a strong Coulomb staircase is visible. The Coulomb blockade is significantly affected by the applied gate voltage. Coulomb oscillations of the blockade width with gate potential are observed.

Fabrication of self-aligned metallic Coulomb blockade devices on Si nanowires

A self-aligned metallic single-electron tunneling transistor was fabricated on a Separated by Implanted Oxygen substrate. An array of 10–50 gold islands of 1–3 nm diameter was isolated between source and drain electrodes on a silicon nanowire. This design reduces the number of transport paths by restricting the number of active nanodots between source and drain. The islands were deposited by a retarding field single ion deposition method, whereby the island sizes and separations could be varied by adjusting landing energy and dose. An undercut beneath the nanowire was used to separate the side gates from the multiple tunnel junction. Coulomb blockade was observed in the source drain characteristics at 77 K.

Single-electron tunnelling transistor in SiGe/Si double-barrier structures

A single-electron transistor (SET) on an SiGe/Si double-barrier structure has been studied with side contact. In Si/SiGe vertical structure transistors we can more easily control the depletion region by gate voltage than in any other three-terminal device. Drain and source regions are one-dimensional and the well region (gate region) of the device is zero-dimensional with reverse gate bias. The resonant tunnelling (one dimension to zero dimension, zero dimension to one dimension) and current-voltage curves are investigated in a two-dimensional quantum model. The effect of delta doping results in shifting and reduction of the peak value of transmission probabilities. We found current enhancement in delta-doped heterostructures at low temperatures. We proved the possibility of an Si single-electron transistor in a two-dimensional simulation of the resonant tunnelling transistor.

Noise Properties of Single Electron Transistors

We have measured the low frequency (5 mHz< f <30 Hz) noise in current biased aluminium single electron tunneling (SET) transistors. A refined high frequency (HF) shielding allows us to maintain and study a given background charge configuration for many hours at T <100 mK. At frequencies below 10 Hz the noise is mainly due to charge traps, and the noise pattern superimposed on the V ( V g )-curve strongly depends on the particular background charge configuration resulting from the cooling sequence and the applied RF irradiation, including thermal radiation from the 4.2 K environment. The noise spectra, which show both 1/ f and 1/ f 1/ 2 dependencies and saturate at f <100 mHz can be fitted by two-level fluctuators (TLF) with Debye–Lorentz spectra and relaxation times on the order of seconds.

Basic mechanisms of an atomic force microscope tip-induced nano-oxidation process of GaAs

An atomic force microscope (AFM) tip-induced direct nano-oxidation process of GaAs(100) substrates has been investigated, and is viewed as a promising method for the fabrication of nanometer-scale electronic devices such as single electron tunneling transistors. The effects of the AFM drawing parameters such as tip bias voltage and writing speed as well as the ambient humidity on the oxide line height and width were explored. The rate of reaction and its dependence on electric field strength and oxide thickness were examined to understand the basic mechanisms involved in the tip-induced oxidation of GaAs. The rate of oxidation/anodization was found to decrease rapidly with oxide film growth, which was explained at the simplest level in terms of a self-limiting influence of decreasing electric field strength.

A new technology for metallic multilayer single electron tunneling devices

A new technology for the fabrication of metallic single electron tunneling (SET) transistors has been developed using different lithography steps for the preparation of the different layers. This offers the possibilty to use different materials and to avoid some disadvantages of the usual shadow evaporation method like unwanted shadows.

Sensing of dynamic charge states using single-electron tunneling transistors

Sensing of dynamic charge states using single-electron tunneling transistors

Nanoscale oxidation of GaAs-based semiconductors using atomic force microscope

Fundamental results obtained in an atomic force microscope (AFM) direct nanoscale oxidation process are presented, which is regarded as a simple method for fabricating nm-scale devices such as single electron tunneling transistors and quantum effect electronic devices. Using Au-coated Si cantilevers, we have succeeded in drawing nm-scale oxide lines in GaAs-based semiconductor surfaces; n+-GaAs(100) and self-assembled InGaAs quantum dots grown by molecular beam epitaxy on GaAs(100) substrates. The effects of AFM drawing parameters such as tip bias voltage and writing speed on oxide linewidth and height have been explored. GaAs oxide lines as narrow as ∼40 nm have been patterned by this technique.

Study of random telegraph signals in a GaAs/AlxGa1 − xAs single electron transistor

A GaAs/AlxGa1−xAs heterointerface contains charge traps, which can capture and emit a single electron stochastically. We study random telegraph signals (RTSs) from these traps using a single electron tunneling (SET) transistor formed in the heterostructure. The output of the SET transistor switches between two states, corresponding to the capture and emission of a single electron. The occurrence of RTS depends on the variation in the potential modified by negatively biased Schottky gates. These gate voltage dependences indicate the spatial positions of traps. Moreover, we investigate the interaction between trappings.

Effect of the electromagnetic environment on Coulomb blockade devices: Model, experiments, and method of analysis

The effect of the electromagnetic environment on Coulomb blockade devices can be estimated through a simple horizon model where the interaction length is determined by the Heisenberg uncertainty principle. The advantage of this horizon model can be demonstrated in a device with two tunnel junctions in parallel where a cutoff voltage related to physical dimensions is observed. This model also explains the characteristics of single junctions and single-electron tunneling (SET) transistors. Several Al/AlO${}_{x}$/Al devices of various geometries were measured and the effective Coulomb barrier has been investigated through the offset voltage defined as ${V}_{\mathrm{off}}\ensuremath{\equiv}V\ensuremath{-}IdV/dI$. We have also used ${V}_{\mathrm{off}}$ to determine the capacitances of SET transistors, from which we determined microstrip capacitance as a function of island size.

Low-frequency noise in single electron tunneling transistor

The noise in current biased aluminium single electron tunneling (SET) transistors has been investigated in the frequency range of 5 mHz&amp;lt;f&amp;lt;30 Hz. A refined high frequency (HF) shielding including resistive coaxial lines, that prevents spurious electromagnetic radiation and especially high energy photons emitted by the 4.2 K environment from reaching the sample, allows us to study a given background charge configuration for many hours below ≈100 mK. The noise at relatively high frequencies originates from internal (presumably thermal equilibrium) charge fluctuations. For f⩾10 Hz, we find the same input charge noise, typically QN=5×10−4 e/Hz1/2 at 10 Hz, with and without the HF shielding. At lower frequencies, the noise is due to charge trapping, and the voltage noise pattern superimposed on the V(Vg) curve (voltage across transistor versus gate voltage) strongly depends on the background charge configuration resulting from the cooling sequence and eventual radio frequency (rf) irradiation. The measured noise spectra which show both 1/f and 1/f1/2 dependencies and saturation for f&amp;lt;100 mHz can be fitted by two-level fluctuators with Debye–Lorentzian spectra and relaxation times of order seconds. In some cases, the positive and negative slopes of the V(Vg) curve have different overlaid noise patterns. For fixed bias on both slopes, we measure the same noise spectrum, and believe that the asymmetric noise is due to dynamic charge trapping near or inside one of the junctions induced when ramping the junction voltage. Dynamic trapping may limit the high frequency applications of the SET transistor. Also reported on are the effects of rf irradiation and the dependence of the SET transistor noise on bias voltage.

Зондирование динамических зарядовых состояний с помощью одноэлектронных туннельных транзисторов

Зондирование динамических зарядовых состояний с помощью одноэлектронных туннельных транзисторов

A silicon Coulomb blockade device with voltage gain

A silicon single electron tunneling transistor (SETT), which shows an inverting voltage gain greater than unity and as high as 3.7, has been fabricated. The blockade voltage as a function of gate voltage shows sawtooth oscillations when biased with a small current and measured at a temperature of 4.2 K. The SETT is fabricated in highly doped and oxidized silicon quantum wires of less than a 40 nm×50 nm cross section and 1.5 μm length.

Modulation of the charge of a single-electron transistor by distant defects

We have systematically measured two-level fluctuator (TLF) noise in a single-electron tunneling transistor. From the amplitude, duty cycle, and presence of intermediate states, we conclude that there is a cluster of triggered TLF's in this case. The systematic dependence of switching rate on gate voltage, and the lack of rate dependence on a finer scale or on source-drain voltage, tell us unambiguously that the TLF's are not located in the tunnel barriers. We thus conclude, as has been previously inferred, that noisy defects outside the barrier can lead to significant modulation of the transistor island charge (up to about 0.2 $e$).

Metallic single electron devices fabricated using a multilayer technique

Single electron tunneling (SET) transistors were fabricated for the electrodes and for the island using two different resist masks. This technology overcomes disadvantages of the well-established shadow evaporation method usually used for the fabrication of SET devices and offers more flexibility in materials and layouts.

Feasibility of a new type of single electron tunneling transistor (SETT) made of high Tc superconductor

Single electron tunneling transistor (SETT) making use of the layered structure of high temperature cuprate superconductors (HTS), is proposed. Also discussed is the statistical probability for the presence of either a single electron or a single electron pair on the island.

Si single electron tunneling transistor with nanoscale floating dot stacked on a Coulomb island by self-aligned process

We fabricated a Si single electron tunneling transistor which has a nanoscale floating dot gate stacked on a Coulomb island by a self-aligned process. This device exhibits drain current (Id) oscillations due to the Coulomb blockade effect and quantized threshold voltage (Vth) shifts resulting from a single electron tunneling from the channel to the floating dot gate. The high on/off current ratio of the Id oscillation combined with the quantized Vth shifts leads to the possibility of developing ultralow power consumption memory.

A Single Electron Neuron Device

A neuron device utilizing the single electron tunneling (SET) effect is described. The device consists of four parts: synaptic weight circuits, a multiplier, an adder, and a nonlinear activation function circuit. The synaptic weight memory is designed with only two turnstiles, and the multiplier and the nonlinear activation function are realized with the use of single electron inverter circuits. The total SET transistor count of a neuron with n inputs is only 6n+2, which is an advantage over a neuron consisting of conventional complementary metal-oxide semiconductor (CMOS) transistors from the viewpoint of occupation area and consumption power. Due to the smallness of the SET neuron, large systems of artificial neural networks could be realized with the use of these devices.