Single-electron Technology Research Articles

Digital Circuits and Systems based on Single-Electron Tunneling Technology

In this work, digital circuits and systems based on single-electron tunneling technology will be presented and analyzed. A simple design methodology will be proposed using a programmable single-electron NAND/NOR gate as a building block. Aspects such as operating temperature, noise, and charge fluctuations will be discussed. SET devices can reach ultra-low power consumption and high frequencies during operation. Although there are already many digital SET circuits and systems previously proposed and studied, there are few works about design methodology for SETs. This study shows a proposal for designing combinational and sequential singleelectron circuits aiming at systems design. In the end, this work reinforces the use of single-electron technology as a possible large scale device in the future.

Performance investigation of nanoscale reversible logic gates designed with SE-TLG Approach

ABSTRACT The progressive shrinking of MOS dimensions confronts critical issues while designing low power consuming computational devices. The Single Electron Technology is one of the emerging technological solutions to cope up with the scaling challenges and support Moore’s law. Apart from the miniaturization, another concern is the energy efficiency of the designed circuit. Use of reversible logic in place of the conventional Boolean logic can serve the purpose. The works so far in this field mainly concentrated upon the application aspect of different reversible gates and reversible circuits rather than proper technological approach or device based design .Different reversible gates such as Fredkin, Toffoli and Double Feynman Gate implementation with Single Electron device and their simulation results are presented in this paper. The power consumption, stability and the size are mainly considered as the different performance metrics. The circuit stability and its temperature dependency is also analysed through the Stability plots generated in SIMON simulator. A new reversible gate PE1 for even parity generating circuits is also proposed along with the supporting simulation results .The design issues and power consumption are compared with the SET-CMOS hybrid-based designs of the same circuits.

English

The very high density of integration and ultra-low power consumption characteristics has given the Single electron devices promising capabilities to replace CMOS transistors in some applications. There are also alternative logic design styles, such as threshold logic, that may be more suitable and also more powerful for novel technologies such as single electron technology. In this paper, we investigate single electron threshold logic gate implementation of some logic circuits, in which the Boolean logic values are encoded as absence or presence of one electron. We present a control unit for a chemical process. Computer based realization of the control unit is performed using SIMON simulation tool. The performance of the simulated model is studied with some sample data and found satisfactory thereby establishing the feasibility of using single electron threshold logic based devices for high future high density low power VLSI/ULSI circuits.

Implementation of 4-bit Reversible Parallel Adder Using Nanoelectronic Single-Electron Circuitry

Single-Electron devices imply the possibility to control the movement and position of a single electron or a few electrons thereby reducing the device size and power consumption. A single-electron transistor can be operated as a switch with the transition of the gate voltage between two appropriate values thereby modifying conventional logic design into the single-electron regime by simply exchanging MOSFETs with SETs. Single-electron logic circuits can thus be employed to perform arithmetic functions, thereby making single-electron technology viable to realize high density low power consumping VLSI circuits. In the present work a single electron logic based high speed power efficient 4-bit reversible binary parallel adder is designed, implemented and its performance studied on its simulated model.

On Single-Electron Technology Full Adders

This paper reviews several full adder (FA) designs in single-electron technology (SET). In addition to the structure and size (i.e., number of devices), this paper tries to provide a quantitative and qualitative comparison in terms of delay, sensitivity to (process) variations, and complexity of the design. This will allow for a better understanding of the advantages and disadvantages of each solution. An optimization of an SET FA (combining one of the SET FAs with a static buffer), together with a new SET FA design (based on capacitive SET threshold logic gates), will also be described and compared with the other SET FAs.

Single-electron charging effects in Si MOS devices

Single-electron charging of small quantum dot structures has been observed for many years. Only recently, however, have the effects been observed in Si device structures suitable for integration into other Si technologies. In this talk, the background of work in Si will be reviewed and its applications to unique device and circuit architectures will be discussed. Experimental results obtained using double-gated quantum dots embedded within a Si MOSFET will be discussed. While the present results are primarily at low temperature, they promise the application of single-electron technology to more integrated circuitry.