Single Digital Signal Processor Research Articles

Design and Implementation of an Integrated Control Scheme for GaN-Based Multiple Power Converters

In response to the rapid changes in the international energy environment, developing renewable energy (RE)-based distributed generation (DG) and various smart micro-grid systems is crucial for creating a robust electric power grid and new energy industries. In this aspect, there is an urgent need to develop hybrid power systems suitable for coexistent AC and DC power grids, integrated by high-performance wide ban gap (WBG) semiconductor-based power conversion interfaces and advanced operating and control strategies. Due to the intrinsic feature of variation in RE-based power generation, the design and integration of energy storage devices, real-time regulation of power flow, and intelligent energy control schemes are key technologies for further promoting DG systems and micro-grids. This paper investigates an integrated control scheme for multiple GaN-based power converters in a small- to medium-capacity, grid-connected, and RE-based power system. This is the first time that a complete design case demonstrating three GaN-based power converters with different control functions integrated with a single digital signal processor (DSP) chip to achieve a reliable, flexible, cost effective, and multifunctional power interface for renewable power generation systems is presented. The system studied includes a photovoltaic (PV) generation unit, a battery energy storage unit, a grid-connected single-phase inverter, and a power grid. Based on system operation condition and the state of charge (SOC) of the energy storage unit, two typical operating modes and advanced power control functions are developed with a fully digital and coordinated control scheme. Hardware of the GaN-based power converters and digital controllers are designed and implemented. The feasibility and effectiveness of the designed controllers and overall performance of the proposed control scheme are verified with results from simulation and experimental tests on a 1-kVA small-scale hardware system.

TiNNA: A Tiny Accelerator for Neural Networks With Efficient DSP Optimization

Accelerators for convolutional neural networks (CNNs) based on field-programmable gate arrays (FPGAs) have drawn much attention in recent years. Two INT-8 multiplications are often implemented on a single digital signal processor (DSP) to improve DSP efficiency and performance. However, most of these works only use DSPs to implement multiplications and do not involve accumulations, which requires a lot of look-up tables (LUTs) and consequently leads to greater energy consumption. Furthermore, these works do not detail how to obtain two signed INT-8 multiplications with a DSP. This brief thus proposes a tiny accelerator for CNNs and a DSP-based processing element (PE) that is designed to implement two signed INT-8 multiply-and-accumulate (MAC) operations to reduce the overhead of LUTs. To allow the DSP to support two signed INT-8 MAC operations and avoid the large loss of accuracy caused by data overflow of partial sums (psum), we apply an efficient DSP optimization approach and a dynamic-precision quantization method. The accelerator is implemented on a Xilinx ZC706 FPGA device and achieves a DSP utilization efficiency <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1.7\times $ </tex-math></inline-formula> to <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$7.3\times $ </tex-math></inline-formula> greater than state-of-the-art accelerators implemented on the same device. Furthermore, our accelerator offers <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$3.56\times $ </tex-math></inline-formula> greater energy efficiency than other FPGA-based accelerators.

Design and Implementation of Convolutional Neural Networks Accelerator Based on Multidie

To achieve real-time object detection tasks with high throughput and low latency, this paper proposes a multi-die hardware accelerator architecture. It implements three accelerators on the VU9P chip, each of which is bound to an independent super logic region (SLR). To reduce off-chip memory access and power consumption, this design uses three on-chip buffers to store the weights and intermediate result data on one hand; on the other hand, it minimizes data access and movement and maximizes data reuse. This design uses an 8-bit quantization strategy for both weights and feature maps to achieve twice the throughput and computational efficiency of a single digital signal processor (DSP). In addition, many operators are designed in the accelerator, and all of them are fully parameterized, so it is easy to extend the network, and the control of the accelerator can be realized by configuring the instruction group. By accelerating the YOLOv4-tiny algorithm, the accelerator architecture can achieve a frame rate of 148.14 frames per second (FPS) and a peak throughput of 2.76 tera operations per second (TOPS) at 200MHz with an energy efficiency ratio of 93.15 GOPS/W. Code is available at https://github.com/19801201/Verilog&#x005F;CNN&#x005F;Accelerator.

Data-Driven Self-sensing Technique for Active Magnetic Bearing

In the last two decades, soft sensors proved themselves as a valuable alternative to the physical sensor for gathering critical process information. A self-sensing technique for the magnetic bearing is considered as a soft sensor since the object position is estimated from the current signal of the electromagnet. Self-sensing techniques developed so far are the model-driven soft sensors. This paper presents a data-driven self-sensing technique to compensate for the nonlinear characteristic of the electromagnet. First, model-driven self-sensing techniques and their problems are reviewed. Then, data-driven self-sensing technique using recurrent neural network (RNN) is proposed to compensate for the nonlinear characteristics. Both the position control and self-sensing with the RNN are implemented in a single digital signal processor. The effectiveness of the proposed method is experimentally verified by comparison with the current slope method. Both estimation errors during initial levitation and jitter after levitation are reduced by 90% and 36%, respectively. Estimation error with 2 Hz sine wave is improved by 65.9%, while jitter during self-sensing levitation is cut down to 26.8%.

An Efficient Method of Parallel Multiplication on a Single DSP Slice for Embedded FPGAs

Field-programmable gate arrays (FPGAs) can efficiently implement custom applications via their embedded digital signal processor (DSP) slices, including binary multipliers. An increasing number of binary multipliers belonging to a DSP slice usually demonstrate that it has the capacity to process as many multiplication operations as possible in one clock cycle. In order to fully utilize the DSP resource, in this paper, we propose a novel DSP slice optimization method to achieve parallel multiplication on single DSP slice, namely PMSDS. First, the PMSDS splits multiplicators into two separate parts, i.e., valid bits and vacant bits, using a customized polynomial algebra method. Then, the PMSDS pre-calculates the maximum number of overflow bits combining the above-mentioned polynomial algebra method. Finally, it computes the total multiplicators' bit numbers and parallel the final multiplicators. We also propose an optimization model to find the best parallel solution according to the performance and precision of a single DSP slice. Moreover, we implement a PMSDS-based matrix multiplication algorithm supporting the computing precision dynamically changing. The experiments based on a large-scale and real-world matrix multiplication show that the PMSDS has better performance in latency and resource utilization than the traditional, add-tree, and full-unroll methods and is more outstanding in frequency and dynamic power consumption comparing with the state-of-the-art methods.

Improved Design and Space Vector Modulation of a Z-Source Ultrasparse Matrix Converter: Analysis, Implementation, and Performance Evaluation

Space vector modulation (SVM) of a Z-source ultrasparse matrix converter (ZSUSMC) can be realized by either using or not using a zero state in the space vector rectification. In this paper, these two modulation schemes are investigated for a cascaded ZSUSMC. It is demonstrated that the input current under the modulation scheme without a zero state is nonsinusoidal, and its harmonics content depends on the output and impedance network inductor currents. In addition, restrictions on operation of the ZSUSMC with low voltage gains are unveiled. Next, aiming at improving the input current quality and suppressing the harmonics content to an acceptable level, an approach for design of the cascaded Z-source network is proposed. Furthermore, an optimal switching pattern, which results in minimum possible number of changes in the switching states of the ZSUSMC, is developed. Using the developed switching pattern, an approach for digital implementation of the SVM schemes on a single conventional digital signal processor (DSP) without employing an additional field programmable gate array is proposed. Hardware-in-the-loop studies of the ZSUSMC modulated under the proposed SVM schemes are carried out to verify their digital implementation feasibility on a conventional single DSP, as well as effectiveness in producing high-quality input/output currents.

Coded Spectral Doppler Imaging: From Simulation to Real-Time Processing.

Transmission of coded pulses and matched receive filtering can improve the ultrasound imaging penetration depth while preserving the axial resolution. This paper shows that the pulse compression technique may be integrated in a low-cost scanner to be profitably used also in spectral Doppler investigations. By operating on beamformed, demodulated, and down-sampled data in the frequency domain, a single digital signal processor is proved sufficient to perform both pulse compression and multigate spectral Doppler algorithms in real time. Simulations, phantom, and in vivo experiments demonstrate that the transmission of (2.5 or [Formula: see text] long) linear frequency-modulated chirps with bandwidths over the range 1.6-5.4 MHz, rather than of corresponding sine-burst pulses, provides signal-to-noise ratio (SNR) improvements very close to theory. Even in the presence of selective tissue attenuation, SNR gains up to 11 and 13.3 dB have been obtained for the short and the longer chirp, respectively. This may be important in clinical Doppler applications where the needed penetration depth is not achieved with sufficient SNR unless very long bursts are transmitted.

A real-time chirp-coded imaging system with tissue attenuation compensation

In ultrasound imaging, pulse compression methods based on the transmission (TX) of long coded pulses and matched receive filtering can be used to improve the penetration depth while preserving the axial resolution (coded-imaging). The performance of most of these methods is affected by the frequency dependent attenuation of tissue, which causes mismatch of the receiver filter. This, together with the involved additional computational load, has probably so far limited the implementation of pulse compression methods in real-time imaging systems.In this paper, a real-time low-computational-cost coded-imaging system operating on the beamformed and demodulated data received by a linear array probe is presented. The system has been implemented by extending the firmware and the software of the ULA-OP research platform. In particular, pulse compression is performed by exploiting the computational resources of a single digital signal processor. Each image line is produced in less than 20μs, so that, e.g., 192-line frames can be generated at up to 200fps.Although the system may work with a large class of codes, this paper has been focused on the test of linear frequency modulated chirps. The new system has been used to experimentally investigate the effects of tissue attenuation so that the design of the receive compression filter can be accordingly guided. Tests made with different chirp signals confirm that, although the attainable compression gain in attenuating media is lower than the theoretical value expected for a given TX Time-Bandwidth product (BT), good SNR gains can be obtained. For example, by using a chirp signal having BT=19, a 13dB compression gain has been measured. By adapting the frequency band of the receiver to the band of the received echo, the signal-to-noise ratio and the penetration depth have been further increased, as shown by real-time tests conducted on phantoms and in vivo. In particular, a 2.7dB SNR increase has been measured through a novel attenuation compensation scheme, which only requires to shift the demodulation frequency by 1MHz. The proposed method characterizes for its simplicity and easy implementation.

A High-Efficiency Single-Stage Low-Power Photovoltaic Inverter System with Maximum Power Point Tracking Control

This paper proposes a single-stage inverter system with maximum power point tracking control (MPPT) applicable in low-power photovoltaic (PV) energy conversion systems. The proposed system is successfully implemented using a single digital signal processor (DSP) TMS320F2808. The proposed single-stage inverter system has the following features: 1) the ability to harvest the maximum PV power using two simple and effective current sampling methods; 2) flexible topology based on the positioning of DC link capacitor on the outside of the inverter bridge circuits; 3) reduced volume and higher efficiency than the conventional two-stage inverters, and 4) MPPT accuracy of 99.3% with overall efficiency of 90% under the full-load condition.

Digital Single-Side Band Modulation Using Digital Signal Processor

Abstract In this paper, we describe the design of a digital single-side band amplitude modulator with 40 kHz output using high-performance digital signal processor for ultrasonic transmitters. The baseband signal is converted to zero-IF signal by using quadrature frequency converter. Then zero-IF signal is filtered by two low-pass filter and converted to output frequency by frequency quadrature up-conversion. It is implemented by using single fixed-point digital signal processor. Experimental result shows that the digital modulation function is well operated, and performance of side-band rejection is better than 50 dB isolation.

Modeling and Control of a Flux-Modulated Compound-Structure Permanent-Magnet Synchronous Machine for Hybrid Electric Vehicles

The compound-structure permanent-magnet synchronous machine (CS-PMSM), comprising a double rotor machine (DRM) and a permanent-magnet (PM) motor, is a promising electronic-continuously variable transmission (e-CVT) concept for hybrid electric vehicles (HEVs). By CS-PMSM, independent speed and torque control of the vehicle engine is realized without a planetary gear unit. However, the slip rings and brushes of the conventional CS-PMSM are considered a major drawback for vehicle application. In this paper, a brushless flux-modulated CS-PMSM is investigated. The operating principle and basic working modes of the CS-PMSM are discussed. Mathematical models of the CS-PMSM system are given, and joint control of the two integrated machines is proposed. As one rotor of the DRM is mechanically connected with the rotor of the PM motor, special rotor position detection and torque allocation methods are required. Simulation is carried out by Matlab/Simulink, and the feasibility of the control system is proven. Considering the complexity of the controller, a single digital signal processor (DSP) is used to perform the interconnected control of dual machines instead of two separate ones, and a typical hardware implementation is proposed.

Optimized Implementation of the FDK Algorithm on One Digital Signal Processor

This paper presents an optimized implementation of the FDK algorithm on a single fixed-point TMS320C6455 digital signal processor (DSP). Software pipelining and proper configuration of the data transfer enables a 2563 volume to be reconstructed in about 42 seconds from 360 projections with very good accuracy. This implementation reveals the potential of modern high-performance DSPs in accelerating image reconstruction, especially when cost and power consumption are emphasized.

A neighbourhood-electric vehicle development with individual traction on rear wheels

A simple traction control implementation of a Neighbourhood Electric Vehicle (NEV) is presented in this paper. An electronic differential traction control is performed using two independent field-oriented controlled Induction Motors (IMs) mounted in the rear wheels. In order to reproduce a mechanical differential behaviour, an equal-torque traction control is carried out using only the IM's currents and speeds measurements. A basic self-blocking control is introduced to avoid uncontrolled wheel acceleration during equal-torque control action. The traction system allows energy recovery for batteries during vehicle braking through the IM's regenerative braking. Standard industrial IMs are rewound to operate on safe low voltage (28 Vrms) and to use standard DC-Link 42V, while maintaining the original motor power. Two three-phase MosFet inverters are built for these motor power requirements. The whole system is controlled using a single digital signal processor, TMS320F2812. Experimental results for different vehicle manoeuvres are presented to validate the right traction control operation.

A software-based receiver running on a single DSP for terrestrial digital multimedia broadcasting

This paper presents the design and implementation of a software (SW)-based receiver running on a single digital signal processor (DSP) for terrestrial digital multimedia broadcasting (TDMB). Implementing the functions of the physical layer such as synchronization and channel decoding as well as codec decoders for a TDMB receiver in software running a DPS raises numerous design and implementation issues. We present solutions to these issues including an efficient software receiver structure, efficient algorithms with low complexity, real-time scheduling, reduction of the execution cycle number, and data transfer and communication between function blocks in the receiver, with a focus on the physical layer. The SW-based TDMB receiver developed in the present work can change and upgrade its functions and adapt to new standards. The performance of the implemented receiver was verified through successful decoding of live audio and video signals.

Design and Implementation of a High-Performance PMLSM Drives Using DSP Chip

This paper presents a digital signal processor (DSP)-based high-performance controller for use in permanent magnet linear synchronous motor (PMLSM) drives. The PMLSM is mathematically modeled and the vector control scheme is used in the current loop of a PMLSM drive. Then, to increase the drive's performance, an adaptive fuzzy controller constructed by a fuzzy basis function and a parameter-adjustable mechanism is derived and applied to the position loop of the PMLSM drive to cope with the dynamic uncertainty and external load effect. Finally, a TMS320F2812 DSP chip produced by Texas Instruments is employed to implement the controller. The new-generation TMS320F2812 exhibits fast computation (150 MIPS) and a completely integrated motor peripheral circuit. Therefore, a fully digital controller for PMLSM drives, in which the current vector control scheme, space vector pulse width modulation generation, A/D conversion, coordinate transformation, quadrature encoder pulse detection, adaptive fuzzy controller, and point-to-point motion controller can be realized within a single DSP chip. An experimental system is established using a PMLSM, a DSP control board, an inverter, a rectifier, and other elements to verify the effectiveness of the proposed high-performance control system. Some experimental results are confirmed theoretically.

FPGA-based implementation of a cavity field controller for FLASH and X-FEL

The subject of this paper is the design and construction of a new generation of superconducting cavity accelerator measurement and control system. The old system is based on a single digital signal processor (DSP). The new system uses a large programmable array circuit (FPGA) instead, with a multi-gigabit optical link. Both systems now work in parallel in the Free Electron Laser in Hamburg (FLASH). The differences between the systems are shown, based on the measurement results of the working machine. The major advantage of the new system is a bigger area of stability of the machine control loop.

New stereo echo canceller operating on single digital signal processor

In this paper, we provide an overview of a new immersive, cost-effective stereo echo canceller that we have developed recently. To achieve immersive stereo hands-free communication, we expanded the frequency range from 0.1–7 kHz to 0.1–20 kHz and revised the echo reduction processing. To achieve a cost-effective canceller, we revised the adaptive algorithm to reduce the required memory and implemented the entire signal processing in a single fixed-point digital signal processor (DSP). The experiments indicate that the new stereo echo canceller delivers near-end speech and background sound more naturally under the double-talk situation.

Fetal descending aorta detailed velocity profiles in real-time using a novel global acquisition & signal processing (G.A.S.P.) software for the multigate spectral doppler analysis

A NOVEL GLOBAL ACQUISITION & SIGNAL PROCESSING (G.A.S.P.) SOFTWARE FOR THE MULTIGATE SPECTRAL DOPPLER ANALYSIS GABRIELE URBAN, PASQUALE PATRIZIO, PIERO TORTOLI, STEFANO RICCI, FABIO SANGUINETI, PATRIZIA VERGANI, MICHAEL PAIDAS, Yale University, Obstetrics & Gynecology, New Haven, Connecticut, University of Florence, Electronic Engineering, Florence, Italy, University of Milano-Bicocca, Monza, Milano, Italy OBJECTIVE: To study velocity profiles, relative wall distension rate (rWDR) of fetal descending aorta (FDA) and shear rate (WSR) in uncomplicated singleton pregnancy. STUDY DESIGN: Eighty Two uncomplicated singleton fetuses were studied at different gestational ages using Multigate Spectral Doppler Analysis (MSDA) working with GASP software. This consists of a PC add-on board including a single high-speed digital signal processor. The analysis of echosignals backscattered from 256 range cells located along the axis of the interrogating ultrasound (US) beam. Post-processing were done using GASP software. Statistical analysis consisted of Spearman correlation and chi-square test. RESULTS: Velocity profiles, wall distension, wall shear rate were obtained from fetal descending aorta at different gestational age. Comparables results from conventional Doppler masks different velocity profiles, turbulent flow (4 cases), downstream (5 cases), partial reverse in diastole (3 cases). WDR[%] is highly correlated with gestational age and fetal growth (2.7G1.8 , rs=0.471 p!0.01) with linear regression with standardized coefficient of 0.4 (p!0.01). Otherwise WSR (432G191) is not significantly variable (P=0.7) from first , second and third trimester. CONCLUSION: This novel technology is more sensitive than conventional Doppler in detecting patterns other than pseudo-laminar flow. The progressive linear increase of wall distansibility detected could be explained by the accumulation of elastin that contributes most to developmental change. The mean WSR for the study group was independent and constant throughout the gestation. This suggest that unless the increase of aortal size adapts to the flow demands and maintain constant the hemodynamic characteristics. The relative WDR changes during gestation, in normal growth, may be secondary to adaptive vascular and autonomic responses and the evolving composition of the vessel wall, particularly with respect to elastin.

A DSP based IP set-top box for home entertainment

In this paper, the implementation of a digital signal processor (DSP) based Internet protocol set-top box for home entertainment networks is described. The main functional blocks are the MPEG-2 transport stream demultiplexer, the audio and video decoders and the audio and video display management modules (with on-screen display capabilities). All blocks have been built into a single low-cost DSP to allow multi-format operation in the future. A prototype has been designed and fully tested in a real environment.

The engineering of supersystems

An everyday mobile phone contains two to four processors executing several hundred million instructions per second (MIPS) in closely coupled or networked configurations that implement the mobile modem as software on a single digital signal processor (DSP). The base stations controlling wireless and wireline communications systems are themselves a hierarchy of closely coupled systems with multiprocessor (typically DSP) subsystems executing billions of instructions per second. A complete base station can incorporate from five to 20 subsystems and 100 separate processors. These supersystems, incorporating possibly dozens of processors in closely coupled or networked topologies, pose a design challenge at least equal to that of designing the component systems and processors. Supersystem design and verification must address hardware complexity that increases with each successive generation of a product family, as well as embedded software content that increases exponentially with time.