Single DC Voltage Source Research Articles

Switched capacitor based 7-level and 9-level multilevel inverters with single DC source and reduced voltage stress

This paper proposes two different switched capacitor based Multilevel Inverter topologies having single dc voltage source. One of the proposed MLIs is a seven-level structure whereas the other circuit successfully generates a nine-level output voltage. The special features of the seven-level topology consist of reduced number of circuit elements, lower voltage stress on switches, and boosted output voltage. The nine-level MLI having unity gain also possess the reduced switch count along with lower value of switch voltage stress. Fundamental frequency based Nearest Level Control modulation and Level-Shifted Pulse Width Modulation have been used for generating the required voltage levels. Successful implementation of the proposed MLI circuits has been done with the help of a laboratory prototype and its results are presented and explained in the paper to show its practical suitability. Other type of analysis include loss analysis which has been done in PLECS software. From this analysis, the efficiency has been estimated. A comparative analysis of both the proposed structures has been carried out with some other similar topologies on different performance parameters. From the analysis and comparison, it is evident that the proposed MLIs are better than some of the existing topologies and can be used for industrial applications.

THD Reduction of Improved Single Source MLI Using Upgraded Black Widow Optimization Algorithm

An upgraded Black Widow Optimization algorithm for obtaining the ideal switching angles of a reduced structure multilevel inverter is proposed in this paper with minimum voltage THD. The conventional BWO algorithm has been modified and proposed to solve the THD minimization problem with faster convergence rate, lesser tuning variables, and lesser number of equations than the other existing nature inspired algorithms. The reduced structure MLI is designed with three asymmetrical DC voltage sources of ratio 1 : 2 : 4 to generate 15-level output voltage which requires reduced number of switching devices in comparison with the existing topologies of equivalent voltage level. The asymmetrical DC voltage sources to the MLI are derived from a single DC voltage source using a multisecondary winding DC-DC converter in order to provide the isolation between the load side and source side. The proposed modified BWO algorithm reduces the complexity of solving the nonlinear equations to achieve the best result by avoiding the local optima. To verify the effectiveness of the upgraded BWO algorithm, the optimization problem for three phase fifteen level MLI has been solved using the genetic algorithm, BFO algorithm, and PSO algorithm. The results for the above three applied algorithms are compared with the upgraded BWO and presented. The proposed algorithm has minimized the output voltage THD to 1.83% at 0.88 modulation index. The developed scheme has been corroborated with the help of MATLAB simulation and the results have been verified through a hardware model developed in laboratory.

A Novel 17-Level Reduced Component Single DC Switched-Capacitor-Based Inverter With Reduced Input Spike Current

Multilevel inverters (MLIs) have become common and resourceful as a result of the fast advancement of technology in the areas of high-voltage and high-power applications, among other things. Recently, MLIs have received a great deal of attention recently, due to the growing need to harness environmentally friendly energy. With reduced power electronics switches, diodes, and a voltage boost gain factor of 8, this article presents a single-phase 17-level switching capacitor inverter design. The proposed inverter uses single dc voltage source, two diodes, 14 power electronics switches, and three capacitors. The different mode of operation of topology is explained in detail, including their self-voltage balancing technique. Additionally, an inductor is used in the capacitor charging loop to avoid current spikes caused by the input dc source while charging the capacitor quickly, thereby increasing capacitor life expectancy significantly. Compared to previously the proposed single-input MLIs, the proposed inverter has a lower semiconductor switch count and a lower cost function value that are its distinguished feature. The performance of the topology is verified by MATLAB/Simulink, and furthermore, a laboratory prototype is utilized, which confirms the feasibility of the proposed topology.

A Switched-Capacitor-Based Six-Level Inverter

This article introduces a new switched-capacitor-based multilevel inverter topology. The proposed structure consists of six switches with a single dc voltage source and three floating capacitors, and it is capable of producing a six-level output voltage waveform with voltage boosting gain of 2.5. Moreover, the voltages of the capacitors are constructively balanced because they are directly charged to fixed voltage by the input dc voltage source. The operating principles, circuit description, and pulsewidth modulation control technique for the proposed topology are presented, along with the selection of components. A comparative study between the proposed inverter and other existing multilevel inverter topologies is also discussed. The simulation results are provided to confirm the theoretical analysis. Furthermore, the experimental results obtained from a laboratory-built prototype under different conditions are presented as a comparison to assess the performance of the proposed inverter.

A Comparative Analysis of Cascaded H-Bridge Multilevel Inverters and Envisaged Topologies

Multilevel inverter circuits are widely used in the field of power generation, power quality devices, energy transmission, etc. Existing MLI have some limitations like a higher percentage of THD and reduced voltage magnitude. In this paper, two different topologies of the cascaded H-bridge MLI are discussed. The first topology uses a single DC voltage source that is shared by all MLI bridges, providing better output results. This topology is the combination of H-bridges connected in parallel at the source side, reducing the voltage sources required. The second topology, on the other hand, does have fewer switches and uses capacitors as a secondary source instead of voltage sources. H-bridges connected in this type of MLI are in series. Such two topologies are designed and simulated in MATLAB simulation software and compared as well. The said article presents a comparison within each topology based on its input DC voltage, percentage THD, Vrms, number of switches, as well as H-bridge prerequisite, among other factors.

A Dumbbell Type (D-Type) multilevel inverter based on switched capacitor concept

ABSTRACT In this paper, a new single-phase seven level inverter with reduced device count is introduced. The structure can boost the input voltage by synthesising the capacitors’ voltages in predetermined current paths. A single DC voltage source is utilised to generate the output AC staircase waveform, which is facilitated via Nearest Level Control. Self-voltage balancing ability, less number of semiconductor devices, high efficiency and control simplicity are the most significant inherent attributes of the proposed circuit. It is also noticeable that in this configuration neither bulky transformer/inductor nor filters are applied. Power loss calculation and required capacitance of the proposed inverter are investigated and theoretical efficiency of 93.31% was reached. Moreover, the proposed converter operates under various load conditions with lower Total Harmonic Distortion compared to recent topologies. Ultimately, operating principles of the proposed D-Type seven-level Inverter and simulation results in MATLAB SIMULINK environment are validated by experimental ones obtained from the laboratory prototype.

A twice boost nine‐level switched‐capacitor multilevel (2B‐9L‐SCMLI) inverter with self‐voltage balancing capability

SummaryThe research on the multilevel inverter structures has been focused on reducing the number of voltage sources and the components while obtaining voltage boosting in the output voltage. A lesser number of components would ensure lesser cost while higher boosting ability increases its application potential. Based on these features, the paper presents a new topology for switched‐capacitor multi‐level inverter (SCMLI), which can produce an output voltage waveform of nine levels with a voltage boosting of twice the input voltage employing a single dc voltage source, three capacitors, and 11 power switches. The operation of switches, capacitors with a self‐charge balancing modulation scheme, and a voltage source for producing nine‐level boosted output voltage make this topology useful, and it is capable of supplying different types of load with efficiency above 97%. The simulation results and the hardware results are provided to verify the satisfactory operation of the proposed topology.

Nine-Level Inverter Based on Resonant Switched-Capacitor and NPP/NPC Unit

By using a single dc voltage source to feed a 4-level switched-capacitor (SC) unit and a 3-level NPP/NPC unit simultaneously, a new 9-level inverter is developed in this work. The 4-level unit is implemented by cascading an inverting half-bridge with a double- or half-mode SC circuit. It involves four transistors, two diodes and two capacitors with self-balanced voltage. Inrush charging current variation <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">di</i> / <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dt</i> of capacitors at switching instants is successfully suppressed by inserting a small inductor into the SC unit. Compared with the existing solutions for 9-level inverters, the proposed circuit has the advantages of simpler structure and lower cost per level. These make the proposed inverter very suitable for low voltage applications such as PV and fuel cells. Circuit configuration, operation, system characteristics under POD-PWM modulation are analyzed in detail. Feasibility and dynamic performance are also demonstrated experimentally.

Three-Phase Step-Up Multilevel Inverter With Self-Balanced Switched-Capacitor

This article presents a new three-phase multilevel inverter with boosting capability for low-voltage applications like electric vehicles and renewable energy sources. This inverter is fed by a single dc voltage source and each phase involves two low-voltage transistors, two high-voltage transistors, two diodes, and two capacitors. Except that the two high-voltage transistors withstand twice the dc input voltage, all other components are rated to the dc input voltage. With phase-disposition pulsewidth modulation, the two types of high- and low-voltage transistors operate in low and high switching frequencies, respectively. This is very beneficial for reducing switching losses and selecting semiconductor switches. The two capacitors are connected in parallel and series alternately with the dc source resulting in high ac output voltage with multiple levels, self-balanced capacitor voltages as well as low voltage ripples. The topology, operation principle, capacitors' voltage ripples and power loss are analyzed in detail. Both simulation and experimental results are provided to demonstrate the feasibility of the proposed inverter.

Deadbeat Control of a Modified Single-Phase Five-Level Photovoltaic Inverter with Reduced Number of Switches

In this article, a modified single-phase five-level photovoltaic inverter is proposed with a single DC voltage source and six semiconductor switches. Compared with the presented inverters, the introduced topology has the advantage of decreased device count and the first switching frequency for high blocking voltage switches. The proposed PV inverter is implemented without clamping diodes and transformers, which leads to a decrement in size and, consequently, the weight of the converter. In addition, for the proposed topology, space vector pulse width modulation (SVPWM) is deployed that reduces the complexity of multilevel modulation. In order to obtain the optimal output voltage of the inverter, the deadbeat controller is suggested as a rapid dynamic, low-computation digital control method. This closed-loop inverter is implemented in TMS320f28335 digital signal controller to evaluate the performance of the proposed inverter under nonlinear and linear loads. Simulation and laboratory prototype results show that IEC 62040-3 harmonic constraints is met for the proposed photovoltaic inverter in standalone applications.

Switched‐capacitor‐based boost multilevel inverter topology with higher voltage gain

This study proposes a new switched-capacitor-based multilevel inverter topology with a single dc voltage source. The proposed topology finds its suitability for renewable energy applications with low voltage. Seven-level (7L) output voltage is achieved across the load with triple-voltage gain employing 2 capacitors and 12 switches. Self-voltage balancing of capacitor voltages, parallel operation of capacitors during discharging mode, reduced voltage stress, and bipolar output voltage generation without using backend H-bridge are the major features of the proposed topology. Furthermore, a generalised structure of the proposed topology has also been discussed here. A comparison with other similar topologies with single-source 7L configuration has been carried out to show the advantages of the proposed topology with reduced switch count. Experimental results have been provided to verify the performance of the proposed topology with different operating conditions.

Reduced voltage stress hybrid multilevel inverter using optimised predictive control

This study presents a hybrid multilevel inverter (HMLI), capable of generating 19 voltage levels using a single DC voltage source. The peak inverse voltage of all the switches is restrained within the input DC source voltage in the proposed HMLI, which requires only three capacitors and 15 switches to achieve 19 voltage levels. In the proposed HMLI, one of the capacitors is self-balanced, while the other two capacitors are balanced using a modified finite control set model predictive control (MFCS-MPC). The proposed MFCS-MPC reduces the computation time considerably without affecting the performance of the system. The proposed HMLI is compared with some other HMLI topologies to show its merits in terms of active and passive components. Finally, the steady-state and dynamic performance of the proposed topology and its control algorithm is validated through simulation and experimentation for a 1 kW prototype.

Modelling of DVR with Artificial Intelligence for Compensate the Voltage Sag, Swell and Flickers by Using SVPWM Switching Techniques in Distribution Lines

In this research proposes FLC and Artificial Neural Network (ANN) based on Dyanamic Voltage Controller (DVR) along with d q o transformation for power qulity improvement in a distribution system. Design a 9levels CHMLI based on Custom Power device with SVPWM techniques. Distribution needs to protect against the harmonics such as sag, swell and flickers are affect on standard pure power supply at the end of the load. These power quality issues are minimised with voltage injection using DVR.The designed inveter to reduced the voltage switching losses and stresses of semiconductor devices. Here used single DC voltage source with a series connection of 4 capacitors for self balancing purpose, 3 diodes,output voltage levels and Cascaded H-bridge cell. the proposed 9 level CHMLI inverter citcuit to helps reducing the number of independent voltage dc sources and IGBTS. The harmonics are less in the output voltage proposed work (new topologies)compared to conventional topology. A comparision of FLC and ANN with THD and Power Factor results and study. It has been carried out to analyse through MATLAB / SIMULINK Software.

A Single Source Transformer-less Boost Multilevel Inverter Topology with Self Voltage Balancing

In this article, a single source transformer-less boost multilevel inverter topology is proposed. The salient features of the proposed topology include voltage boost capability, reduced number of switches, and requirement of a single dc voltage source, which in turn reduces the overall cost and complexity. The proposed topology comprises a conventional boost converter and a diode–capacitor voltage multiplier circuit (VMC). The capacitors’ voltages of the VMC are self-balanced, which eliminates the requirement of any auxiliary circuit for capacitor voltage balancing. Moreover, due to the input inductor, it has less input current ripple and able to provide variable fractional voltage gain, which is a key requirement for maximum power point tracking in photovoltaic applications. In order to get an optimal harmonic profile of the output ac voltage, a fundamental frequency switching technique named as the fundamental frequency sine quantization method is adopted for the generation of the switching signals. Finally, a hardware prototype of the proposed 11-level boost inverter is developed and the experimental results along with the MATLAB/Simulink results are presented to validate the efficacy of the proposed converter.

Design and Control of Space Vector Pwm Technique with the Fuzzy Control Based Multilevel Inverter for an Open end Winding Induction Motor

In this paper the three phase open end winding IM drive is designed and controlled using a fuzzy control based multilevel inverter with SVM technique is proposed. To overcome the disadvantages of PI controller, in this project we are using the fuzzy controller. The fuzzy controller rules are analyzed very easily, because of it is a human decision making system. The traditional dual inverter having two dc sources the cost and size is might be high, so to overcome this we use the proposed method with single dc voltage source. The main objective of the proposed method is to eliminate the transformer. To achieve the multilevel output voltage waveform with three levels a dc voltage ratio 2:1 is used. The space vector PWM is used to control the switching states of dual multilevel inverter. The fuzzy controller implementation cost is less and more precise. The simulation results are used to analyze the proposed method with fuzzy controller.

A Novel Deadbeat Predictive Current Control Scheme for OEW-PMSM Drives

In an open-end winding permanent magnet synchronous machines drive with single dc voltage source, zero-sequence current (ZSC) can lead to a high current stress of power modules and loss of motor. Therefore, some modulation strategies have been employed to alleviate ZSC by suppressing zero-sequence voltage (ZSV). However, ZSC still exists in the system because ZSV can also be generated by other nonlinear factors of inverter such as the dead time of system. In addition, zero-sequence back electromotive force in the zero-sequence path can also enlarge torque ripple and ZSC. In order to deal with above problems, first, this paper proposes a full-order adaptive zero-sequence observer to estimate future ZSC and ZSV, which are able to compensate one-step control delay. Second, to achieve the maximum voltage dc bus utilization, this paper proposes a novel deadbeat predictive current control (DPCC) scheme with alternate sub-hexagonal center pulsewidth modulation strategy to suppress ZSC and torque ripple simultaneously. Finally, this paper presents a comparative study of two types of methods, namely traditional DPCC scheme and the proposed DPCC scheme. Simulation and experimental results are demonstrated to verify the effectiveness of the proposed DPCC scheme.

Improved Finite-State Model Predictive Current Control With Zero-Sequence Current Suppression for OEW-SPMSM Drives

In order to suppress zero-sequence current (ZSC) for open-end winding surfaced permanent magnet synchronous machine (OEW-SPMSM) drives with single dc voltage source, many methods have been employed. Actual solutions imply either proportional-integral-based control or direct torque control cannot present the characteristic of fast dynamic responses and low torque ripples at the same time. Hence, finite-state model predictive current control (FS-MPCC) based on a cost function with ZSC suppression was proposed. To suppress model parameter mismatch, many previous works have proposed related strategies but few work considered zero-sequence parameter disturbances such as zero-sequence inductance, resistance, and rotor flux linkage disturbances. This article improves the ZSC prediction model based on the previous ZSC errors and zero-sequence voltage deviations, and at the same time ZSC is reduced. A comparison between the conventional FS-MPCC and the improved one is carried out in simulation and experiment to verify the effectiveness of the proposed FS-MPCC scheme.

A New Switched Capacitor 7L Inverter With Triple Voltage Gain and Low Voltage Stress

In this brief, a new switched capacitor based multilevel inverter topology is proposed. The proposed topology generates seven level (7L) output voltage using a single dc voltage source along with two floating capacitors. The output voltage of the proposed topology is three-times higher than the input voltage (i.e., gain factor of $\text{V}_{\mathrm{ in}}$ : $\text{V}_{\mathrm{ out}} = 1:3$ ) along with self-voltage balancing of capacitors. The proposed seven level triple voltage gain boost inverter (7L-3GBI) inherently generates a bipolar waveform without backend H-bridge that reduces the total standing voltage of the topology. The practicability of the proposed topology has been demonstrated by having a quantitative and cost comparison with similar topologies. Furthermore, the workability of the proposed 7L topology has been validated through different results taken from a prototype laboratory setup.

A transformerless topology for a micro inverter with elevation factor of 1:10 for photovoltaic applications

In this paper, a modified transformerless inverter topology for photovoltaic (PV) applications is presented. This proposal is capable to produce a nine-level AC output from a single low DC voltage source with an efficiency of 95.59%, making it ideal as a micro-inverter. This is achieved by an elevation phase that generates two isolated DC outputs from a single source, using a redesigned DC/DC parallel boost converter that elevates up to ten times the input with no extreme duty cycles and performing it with fewer components compared to similar capacities topologies.These two isolated voltages are employed to feed an asymmetrical cascade cells DC/AC inverter. The theoretical fundaments and both simulation and experimental results presented in this paper validate the proposed topology.

Parallel Connected VSI Inverter using Multi-carrier based Sinusoidal PWM Technique

This paper explains the simulation and modelling of Parallel operation of VSI inverter using multi-carrier based PWM technique. By this proposed method three level inverter output voltages generated instead of using multilevel inverter or two level dual VSI inverter. This system employs single dc voltage source, which gives supply to both VSI inverter by using parallel connection. The multi-carrier based pulse width modulation technique affianced to control the inverter power switches. The proposed system offers improved output voltage, better current control and reduced harmonic distortion. The simulation results of this proposed system was verified using matlab/simulink.