Low temperature electron spin resonance studies have been carried out on single crystalline arrays of sub-10 nm Si nanowires (NWs) manufactured on (100)Si by top down etching and oxidation thinning. This reveals the presence of a substantial inherent density of Pb0 (Si3 ≡ Si•) defects (traps) at the NW Si/SiO2 interfaces, due to particular faceting and enhanced interface strain, leaving NW interfaces of reduced electrical quality. Perusal of the specific properties of the occurring Pb-type defect system points to a nanopillar morphology compatible with NWs predominantly bordered by {110} facets, with cross sectional shape of 〈100〉 truncated {110} squares. The inherent interface quality appears limited by the wire-narrowing thermal oxidation procedure.