Single-core Processors Research Articles

MIMO-OFDM LTE system based on a parallel IFFT/FFT on NoC-based FPGA

The growing demand for wireless devices capable of performing complex communication processes has imposed an urgent need for high-speed communication systems and advanced network processors. This paper proposes a hardware workflow developed for the Long-Term Evolution (LTE) communication system. It studies the multiple-input, multiple-output orthogonal frequency-division multiplexing (MIMO-OFDM) LTE system. Specifically, this work focuses on the implementation of the OFDM block that dominates the execution time in high-speed communication systems. To achieve this goal, we have proposed an NoC-based low-latency OFDM LTE multicore system that leverages Inverse Fast Fourier Transform (IFFT) parallel computation on a variable number of processing cores. The proposed multicore system is implemented on an FPGA platform using the ProNoC tool, an automated rapid prototyping platform. Our obtained results show that LTE OFDM execution time is drastically reduced by increasing the number of processing cores. Nevertheless, the NoC’s parameters, such as routing algorithm and topology, have a negligible influence on the overall execution time. The implementation results show up to 24% and 76% execution time reduction for a system having 2 and 16 processing cores compared to conventional LTE OFDM implemented in a single-core, respectively. We have found that a 4×4 Mesh NoC with XY deterministic routing connected to 16 processing tiles computing IFFT task is the most efficient configuration for computing LTE OFDM. This configuration is 4.12 times faster than a conventional system running on a single-core processor.

Performance Assessment of the CCSDS-123 Standard for Panchromatic Video Compression on Space Missions

The use of next-generation and high-resolution imaging sensors is gaining interest for space missions, because of their properties for identification and exploration purposes. It is expected that the demand for video sensors in the space industry will increase during the next years, mainly for monitoring and exploration missions. In this context, onboard video compression techniques emerge as mandatory, because memory resources are available on space missions and the downlink bandwidth with ground prevents for the transmission of raw video, especially when near real-time capabilities are required. The complexity of the current commercial video encoders supposes a challenge for their implementation on the hardware used on space missions, because of their high architectural complexity and computational requirements, deriving in an area overhead and an unacceptable power consumption. In this context, we propose the use of the CCSDS-123.0-B-2 standard, originally focused on the near-lossless on-board compression of multispectral and hyperspectral images, for compressing panchromatic video. The proposed solution presents low complexity, because it is specifically designed for working on space missions and also has the capability of compressing both 3-D images and panchromatic video by using a single processing core. Results demonstrate that this solution achieves high compression ratios, maintaining a considerable video quality after reconstruction on ground and achieving a fine-grain control of the losses introduced in the compression chain.

Flexibility and rigidity index for chromosome packing, flexibility and dynamics analysis

The packing of genomic DNA from double helix into highly-order hierarchical assemblies has a great impact on chromosome flexibility, dynamics and functions. The open and accessible regions of chromosomes are primary binding positions for regulatory elements and are crucial to nuclear processes and biological functions. Motivated by the success of flexibility-rigidity index (FRI) in biomolecular flexibility analysis and drug design, we propose an FRI-based model for quantitatively characterizing chromosome flexibility. Based on Hi-C data, a flexibility index for each locus can be evaluated. Physically, flexibility is tightly related to packing density. Highly compacted regions are usually more rigid, while loosely packed regions are more flexible. Indeed, a strong correlation is found between our flexibility index and DNase and ATAC values, which are measurements for chromosome accessibility. In addition, the genome regions with higher chromosome flexibility have a higher chance to be bound by transcription factors. Recently, the Gaussian network model (GNM) is applied to analyze the chromosome accessibility and a mobility profile has been proposed to characterize chromosome flexibility. Compared with GNM, our FRI is slightly more accurate (1% to 2% increase) and significantly more efficient in both computational time and costs. For a 5Kb resolution Hi-C data, the flexibility evaluation process only takes FRI a few minutes on a single-core processor. In contrast, GNM requires 1.5 hours on 10 CPUs. Moreover, interchromosome interactions can be easily combined into the flexibility evaluation, thus further enhancing the accuracy of our FRI. In contrast, the consideration of interchromosome information into GNM will significantly increase the size of its Laplacian (or Kirchhoff) matrix, thus becoming computationally extremely challenging for the current GNM. The software and supplementary document are available at https://github.com/jiajiepeng/FRI_chrFle .

An Advanced Dynamic Visualization Method of Global Ocean Tide with Multi-core Processor Based on OpenGL

Abstract. In terms of ocean tide visualization, to meet the requirement of both display range and operational efficiency, an advanced method is proposed, in which the tide height is rapidly computed with global tide model EOT10a, and dynamically displayed by OpenGL. Aiming at the large amounts of calculation of global tide height, the feature of multicore processor is integrated into the method. The experiment shows that, compared to a single-core processor, when using a 6-core processor, the speedup ratio is about 5.4, parallel efficiency reaches 90%, and 880 000 tide heights can be calculated per second. Eventually, the result would be output as a tide height graph by OpenGL. This method could be a useful tool for marine cartography due to the large display range and the high efficiency.

A scalable solver for a stochastic, hybrid cellular automaton model of personalized breast cancer therapy.

Mathematical modeling and simulation is a promising approach to personalized cancer medicine. Yet, the complexity, heterogeneity and multi-scale nature of cancer pose significant computational challenges. Coupling discrete cell-based models with continuous models using hybrid cellular automata (CA) is a powerful approach for mimicking biological complexity and describing the dynamical exchange of information across different scales. However, when clinically relevant cancer portions are taken into account, such models become computationally very expensive. While efficient parallelization techniques for continuous models exist, their coupling with discrete models, particularly CA, necessitates more elaborate solutions. Building upon FEniCS, a popular and powerful scientific computing platform for solving partial differential equations, we developed parallel algorithms to link stochastic CA with differential equations (https://bitbucket.org/HTasken/cansim). The algorithms minimize the communication between processes that share CA neighborhood values while also allowing for reproducibility during stochastic updates. We demonstrated the potential of our solution on a complex hybrid cellular automaton model of breast cancer treated with combination chemotherapy. On a single-core processor, we obtained nearly linear scaling with an increasing problem size, whereas weak parallel scaling showed moderate growth in solving time relative to increase in problem size. Finally, we applied the algorithm to a problem that is 500 times larger than previous work, allowing us to run personalized therapy simulations based on heterogeneous cell density and tumor perfusion conditions estimated from magnetic resonance imaging data on an unprecedented scale.

A novel approach based on genetic algorithm to speed up the discovery of classification rules on GPUs

This paper proposes a new approach to produce classification rules based on evolutionary computation with novel crossover and mutation operators customized for execution on graphics processing unit (GPU). Also, a novel method is presented to define the fitness function, i.e. the function which measures quantitatively the accuracy of the rule. The proposed fitness function is benefited from parallelism due to the parallel execution of data instances. To this end, two novel concepts; coverage matrix and reduction vectors are used and an altered form of the reduction vector is compared with previous works. Our CUDA program performs operations on coverage matrix and reduction vector in parallel. Also these data structures are used for evaluation of fitness function and calculation of genetic operators in parallel. We proposed a vector called average coverage to handle crossover and mutation properly. Our proposed method obtained a maximum accuracy of 99.74% for Hepatitis C Virus (HCV) dataset, 95.73% for Poker dataset, and 100% for COVID-19 dataset. Our speedup is higher than 20% for HCV and COVID-19, and 50% for Poker, compared to using single core processors.

Implementation Parallel Computation for Automatic Clustering

Developments in the industrial world, especially in the field of computer technology, demand solutions to needs ranging from computing resources, storage media, and communication speeds. This was followed by many new studies in this field, including those related to clustering. Clustering is an exploratory data analysis tool that deals with the task of grouping objects that are similar to each other [1], [2]. Clustering requires computers with high resources, usually the price for computers with high resources, while computers with not too high specifications will be less reliable in handling such large data. Clustering that runs on a single-core processor takes a long time to execute tasks, so parallel computing is needed to speed up computing performance especially at Automatic Clustering. This research will produce faster performance in grouping large data by utilizing parallel computing and automatic clustering methods as methods for grouping data. This technology allows data processing to be carried out in parallel and distributed in hundreds or even thousands of computers, so this technology is very appropriate for processing very large amounts of data)

Multi-rate Real Time Hybrid Simulation operated on a flexible LabVIEW real-time platform

This paper presents a real-time hybrid simulation (RTHS) strategy where the numerical and experimental substructures are executed at two different rates to optimize computational resources while maintaining an effective actuator control. The concept is referred to here as multi-rate real-time hybrid simulation (mrRTHS), and this approach is intended to enable low-cost RTHS by facilitating testing in the case of limited computational resources. Operated on a Laboratory Virtual Engineering Workshop (LabVIEW) real-time target, the mrRTHS concept is demonstrated through both a single- and multipledegree-of-freedom (SDOF) and (MDOF) mass-spring-damper system. The numerical substructure generates a displacement signal with a coarse time step of Δt. Using the current and three previous displacement data points, a finer control signal is defined with a time step of δt, using a third-order polynomial algorithm–referred to here as the polynomial fitting extrapolator. Both the numerical substructure and polynomial fitting extrapolator is executed with a sampling rate of Δt by an on-board single-core processor–referred to here as the digital signal processor (DSP). Through a field-programmable gate array (FPGA) the control signal is compensated and transmitted to the transfer system through an I/O module with a sampling rate of 1 kHz (i.e. δt = 0.001 sec). The ratio between Δt and δt are an integer–referred to here as the execution ratio. For an execution ratio of 1:5 and 1:10 the system performance is evaluated against a numerical model of the emulated structure–referred to here as the reference structure. For both the SDOF and MDOF system, a good correlation between the mrRTHS and reference is achieved with execution ratios of 1:5 and 1:10. When changing the execution ratio from 1:5 to 1:10, approximately 50% reduction of the required computational resources on the DSP is achieved.

Design and implementation of dual-core MIPS processor for LU decomposition based on FPGA

Many systems like the control systems and in communication systems, there is usually a demand for matrix inversion solution. This solution requires many operations, which makes it not possible or very hard to meet the needs for real-time constraints. Methods were exists to solve this kind of problems, one of these methods by using the LU decomposition of matrix which is a good alternative to matrix inversion. The LU matrices are two matrices, the L matrix, which is a lower triangular matrix, and the U matrix, which is an upper triangular matrix. In this paper, a design of dual-core processor is used as the hardware of the work and certain software was written to enable the two cores of the dual-core processor to work simultaneously in computing the value of the L matrix and U matrix. The result of this work are compared with other works that using single-core processor, and the results found that the time required in the cores of the dual-core is more less than using single-core. The designed dual-core processor is invoked using the VHDL language.

Synchronized Motion Profiles for Inverse-Dynamics-Based Online Control of Three Inextensible Segments of Trunk-Type Robot Actuators

This study proposes a novel method for the positioning and spatial orientation control of three inextensible segments of trunk-type robots. The suggested algorithm imposes a soft constraint assumption for the end-effector’s endpoint and a mandatory constraint on its direction. Simultaneously, the algorithm by-design enforces nonholonomic features on the robot segments in the form of arcs. An approximate robot spine curve is the key to the final robot state configuration based on the given conditions. The numeric simulation showed acceptable (less than 1 s) performance for single-core processing tasks. The parametric method finds the best proximate robot state solution and represents the gray box model in addition to existing learning or black-box inverse dynamics approaches. This study also shows that a multiple inverse kinematics answer constructs a single inverse dynamics solution that defines the robot actuators’ motion profiles, synchronized in time. Finally, this text presents rotational expressions and their outlines for controlling the manipulator’s tendons.

Dynamic Frequency Scaling for Low-Power Operation of a Single-Core Processor: A Radial Basis Function Approach

Dynamic frequency scaling (DFS) is one of the most important approaches to saving power in modern day processors. With ever-increasing complexity at system, circuit and device levels, the problem of achieving an efficient DFS boils down to multi-parametric nonlinear optimization. Therefore, it is imperative to explore ingenuous approaches to DFS which could identify an optimal underclocking frequency on-the-fly using an adaptive mechanism. This paper proposes an offline neural network approach to DFS of a ubiquitous single-core processor where several performance parameters of the processor were monitored under application of a number of clocking frequencies. The dataset thus generated was used to train two classifiers, viz. the radial basis function network and the probabilistic neural network. Under changing parametric conditions of the proposed network, the model was fit to performance-monitoring data while running 64-point and 1024-point FFT applications, and one benchmark application named basicmath. To demonstrate the generalization of the classifiers, the models were trained offline by the dataset obtained by clubbing the aforementioned applications. The performance of both the classifiers was found to be promising, and good generalization was obtained with all the datasets. The results indicate toward suitability of trained radial basis family of networks for on-chip deployment for implementing on-the-fly DFS.

Scalable Bayesian inference for self-excitatory stochastic processes applied to big American gunfire data.

The Hawkes process and its extensions effectively model self-excitatory phenomena including earthquakes, viral pandemics, financial transactions, neural spike trains and the spread of memes through social networks. The usefulness of these stochastic process models within a host of economic sectors and scientific disciplines is undercut by the processes' computational burden: complexity of likelihood evaluations grows quadratically in the number of observations for both the temporal and spatiotemporal Hawkes processes. We show that, with care, one may parallelize these calculations using both central and graphics processing unit implementations to achieve over 100-fold speedups over single-core processing. Using a simple adaptive Metropolis-Hastings scheme, we apply our high-performance computing framework to a Bayesian analysis of big gunshot data generated in Washington D.C. between the years of 2006 and 2019, thereby extending a past analysis of the same data from under 10,000 to over 85,000 observations. To encourage widespread use, we provide hpHawkes, an open-source R package, and discuss high-level implementation and program design for leveraging aspects of computational hardware that become necessary in a big data setting.

Deep Learning-Based Short-Term Load Forecasting Approach in Smart Grid With Clustering and Consumption Pattern Recognition

Different aggregation levels of the electric grid’s big data can be helpful to develop highly accurate deep learning models for Short-term Load Forecasting (STLF) in electrical networks. Whilst different models are proposed for STLF, they are based on small historical datasets and are not scalable to process large amounts of big data as energy consumption data grow exponentially in large electric distribution networks. This paper proposes a novel hybrid clustering-based deep learning approach for STLF at the distribution transformers’ level with enhanced scalability. It investigates the gain in training time and the performance in terms of accuracy when clustering-based deep learning modeling is employed for STLF. A k-Medoid based algorithm is employed for clustering whereas the forecasting models are generated for different clusters of load profiles. The clustering of the distribution transformers is based on the similarity in energy consumption profile. This approach reduces the training time since it minimizes the number of models required for many distribution transformers. The developed deep neural network consists of six layers and employs Adam optimization using the TensorFlow framework. The STLF is a day-ahead hourly horizon forecasting. The accuracy of the proposed modeling is tested on a 1,000-transformer substation subset of the Spanish distribution electrical network data containing more than 24 million load records. The results reveal that the proposed model has superior performance when compared to the state-of-the-art STLF methodologies. The proposed approach delivers an improvement of around 44% in training time while maintaining accuracy using single-core processing as compared to non-clustering models.

Parallelization Technique using Hybrid Programming Model

A multi-core processor is an integrated circuit that contains multiple core processing unit. For more than two decades, the single-core processors dominated the computing environment. The continuous development of hardware and processors led to the emergence of high-performance computers that able to address complex scientific and engineering programs quickly. Besides, running the software codes sequentially increases the execution time in huge and complex programs. The serial code is converted to parallel code to improve the program perfor-mances and reduce the execution time. Therefore, parallelization helps programmers solve computing problems efficiently. This study introduced a novel automatic translation tool that converts serial C++ code into a hybrid parallel code. The study analyzed the performance of the proposed S2PMOACC tool using linear algebraic dense matrix multiplication benchmarking. Besides, we introduced Message Passing Interface (MPI) + Open Accelerator (OpenACC) as a hybrid programming model without preliminary knowledge of parallel programming models and dependency analysis of their source code. The research outcomes enhance the program performances and decrease the implementation time. Moreover, our proposed technique offers better performance than other tools.

Learning-based BTI stress estimation and mitigation in multi-core processor systems

With the increasing demand of designing a reliable processing devices, the issue of CMOS ageing is jeopardising the industry of digital devices. Many studies has been cover this area for modelling the ageing behaviour at the device level or developing ageing sensors for on-line delay detection at the system level. However, we are presenting a method to estimate the ageing stresses (e.g. Temperature, Ageing Stress Activity) rather than the modelling ageing (performance degradation) itself. The purpose for estimating the ageing stress is to optimise the system utilisation with the minimisation of ageing stress. In multicore processors, the existence of more than one source of ageing stress is higher than single core processor but the optimisation space is higher as well along with the temperature and power optimisation. In this paper, we have modelled the ageing stress from the application level using machine learning techniques to train data extracted from high level workloads ( e.g. parsec and splash2 benchmarks) on four cores processor from Xeon. The ageing stress model is able to estimate the ageing stress with 0.1% error and is able to proactively reduce the ageing stress by 50%.

Rapid generation of optimal generalized Monkhorst-Pack grids

Computational modeling of the properties of crystalline materials has become an increasingly important aspect of materials research, consuming hundreds of millions of CPU-hours at scientific computing centers around the world each year, if not more. A routine operation in such calculations is the evaluation of integrals over the Brillouin zone. We have previously demonstrated that performing such integrals using generalized Monkhorst-Pack k-point grids can roughly double the speed of these calculations relative to the widely-used traditional Monkhorst-Pack grids. However the generation of optimal generalized Monkhorst-Pack grids is not implemented in most software packages due to the computational cost and difficulty of identifying the best grids. To address this problem, we present new algorithms that allow rapid generation of optimal generalized Monkhorst-Pack grids on the fly. We demonstrate that the grids generated by these algorithms are on average significantly more efficient than those generated using existing algorithms across a range of grid densities. For grids that correspond to a real-space supercell with at least 50 Å between lattice points, which is sufficient to converge density functional theory calculations within 1 meV/atom for nearly all materials, our algorithm finds optimized grids in an average of 0.19 s on a single processing core. To facilitate the widespread adoption of this approach, we present new open-source tools including a library designed for integration with third-party software packages.

A Preliminary Study on the Use of the Linear Regression Method for Multigroup Cross-Section Interpretation

Computational modeling and simulations are widely used for evaluation of the performance and safety features of innovative nuclear reactor designs. Multigroup-based deterministic neutronics codes are often employed in these reactor design calculations because they can provide fast predictions of the neutron flux distribution and other neutronics characteristic parameters. Nevertheless, providing accurate multigroup cross sections for deterministic codes is an onerous job, which makes establishing an exhaustive cross-section library computationally prohibitive. Partly because of these reasons, multigroup neutron cross sections are normally stored only at certainty state points in the data library of these deterministic codes, and linear interpolation methodology is commonly utilized to estimate the cross sections at unknown states. However, the applicability of linear interpolation is limited, and the precision of its results is moderate. In this paper, we discuss a preliminary feasibility study that we performed on providing more precise multigroup cross sections for deterministic neutronics codes by using the linear regression methodology. Compared to the traditional linear interpolation method, the linear regression approach principally showed improved computational efficiency considering the use of more data in the cross-section library, and constructed hypothesis functions for the responses of interest with a higher order of accuracy. In this study, a case study on Lightbridge Corporation’s metallic fuel element was carried out to demonstrate the feasibility and advantages of linear regression in multigroup cross-section interpretation. A reference cross-section library was established through calculations conducted with the Monte Carlo neutronic code Serpent. Because of the preliminary nature of this feasibility study, only the macroscopic total cross section is considered. Linear interpolation and linear regression were both used to estimate cross sections at unknown states based on the data available in the library. By comparing the performance of both methodologies, we demonstrated that the linear regression methodology achieved wider applicability and better precision in cross-section interpretation. Moreover, the linear regression process was finished within 15 s using a single processor core, which indicated that the additional computational burden brought by the implementation of linear regression methodology in the task was acceptable.

An OpenGL Compliant Hardware Implementation of a Graphic Processing Unit Using Field Programmable Gate Array–System on Chip Technology

FPGA-SoC technology provides a heterogeneous platform for advanced, high-performance systems. The System on Chip (SoC) architecture combines traditional single and multiple core processor topologies with flexible FPGA fabric. Dynamic reconfiguration allows the hardware accelerators to be changed at run-time. This article presents a novel OpenGL compliant GPU design implemented on an FPGA. The design uses an FPGA-SoC environment allowing the embedded processor to offload graphics operation onto a more suitable architecture. To the authors’ knowledge, this is a first. The graphics processor consists of GLSL compliant shaders, an efficient Barycentric Rasterizer, and a draw mode manager. Performance analysis shows the throughput of the shaders to be hundreds of millions of vertices per second. The design uses both pipelining and resource reuse to optimise throughput and resource use, allowing implementation on a low-cost, FPGA device. Pixel processing rates from this implementation are almost 80% higher than other FPGA implementations. Power consumption compared with comparative embedded devices shows the FPGA consuming as little as 2% of the power of a Mali device, and an up to 11.9-fold increase in efficiency compared to an Nvidia RTX 2060 - Turing architecture device.

Achieving reliable UDP transmission at 10 Gb/s using BSD socket for data acquisition systems

User Datagram Protocol (UDP) is a commonly used protocol for data transmission in small embedded systems. UDP as such is unreliable and packet losses can occur. The achievable data rates can suffer if optimal packet sizes are not used. The alternative, Transmission Control Protocol (TCP) guarantees the ordered delivery of data and automatically adjusts transmission to match the capability of the transmission link. Nevertheless UDP is often favored over TCP due to its simplicity, small memory and instruction footprints. Both UDP and TCP are implemented in all larger operating systems and commercial embedded frameworks. In addition UDP also supported on a variety of small hardware platforms such as Digital Signal Processors (DSP) Field Programmable Gate Arrays (FPGA). This is not so common for TCP. This paper describes how high speed UDP based data transmission with very low packet error ratios was achieved. The near-reliable communications link is used in a data acquisition (DAQ) system for the next generation of extremely intense neutron source, European Spallation Source. This paper presents measurements of UDP performance and reliability as achieved by employing several optimizations. The measurements were performed on Xeon E5 based CentOS (Linux) servers. The measured data rates are very close to the 10 Gb/s line rate, and zero packet loss was achieved. The performance was obtained utilizing a single processor core as transmitter and a single core as receiver. The results show that support for transmitting large data packets is a key parameter for good performance. Optimizations for throughput are: MTU, packet sizes, tuning Linux kernel parameters, thread affinity, core locality and efficient timers.

Dynamic Frequency Scaling of a Single-Core Processor Using Machine Learning Paradigms

Abstract Dynamic frequency scaling (DFS) is one of the most important approaches for on-the-fly power optimization in modern-day processors. Owing to the trend of chip size shrinkage and increasing the complexity of system design, the problem of achieving an efficient DFS depends upon multi-parametric, non-linear optimization. Hence, it becomes extremely important to identify an optimal underclocking frequency on-the-fly, which depends upon numerous parameters that do not share direct relationship amongst each other. This paper proposes a machine learning approach to DFS of a ubiquitous single-core processor. Several performance parameters of the processor were monitored under an application of a number of clocking frequencies. The dataset thus generated was used to train four artificial neural networks (ANNs) viz. generalized regression (GRNN), decision tree classifier, random forest classifier and backpropagation technique. Under changing parametric conditions of the proposed network, the modes were fit to data while running three applications, i.e. 64- and 1024-point fast fourier transform (FFT) and basicmath applications. The performance of all ANNs was found to be promising and good generalization was obtained with all datasets. In the view of optimizing both speed and power of a system, the results indicate towards suitability of trained GRNN for on-chip deployment for implementing DFS.