Single-core Platforms Research Articles

Vectorized and Parallel Computation of Large Smooth-Degree Isogenies using Precedence-Constrained Scheduling

Strategies and their evaluations play important roles in speeding up the computation of large smooth-degree isogenies. The concept of optimal strategies for such computation was introduced by De Feo et al., and virtually all implementations of isogeny-based protocols have adopted this approach, which is provably optimal for single-core platforms. In spite of its inherent sequential nature, several recent works have studied ways of speeding up this isogeny computation by exploiting the rich parallelism available in vectorized and multi-core platforms. One obstacle to taking full advantage of this parallelism, however, is that De Feo et al.’s strategies are not necessarily optimal in multi-core environments. To illustrate how the speed of vectorized and parallel isogeny computation can be improved at the strategylevel, we present two novel software implementations that utilize a state-of-the-art evaluation technique, called precedence-constrained scheduling (PCS), presented by Phalakarn et al., with our proposed strategies crafted for these environments. Our first implementation relies only on the parallelism provided by multi-core processors. The second implementation targets multi-core processors supporting the latest generation of the Intel’s Advanced Vector eXtensions (AVX) technology, commonly known as AVX-512IFMA instructions. To better handle the computational concurrency associated with PCS, we equip both implementations with extensive synchronization techniques. Our first implementation outperforms the implementation of Cervantes-Vázquez et al. by yielding up to 14.36% reduction in the execution time, when targeting platforms with two- to four-core processors. Our second implementation, equipped with four cores, achieves up to 34.05% reduction in the execution time compared to the single-core implementation of Cheng et al. of CHES 2022.

A systematic methodology to migrate complex real-time software systems to multi-core platforms

This paper proposes a systematic three-stage methodology for migrating complex real-time industrial software systems from single-core to multi-core computing platforms. Single-core platforms have limited computational capabilities that prevent integration of computationally demanding applications such as image processing within the existing system. Modern multi-core processors offer a promising solution to address these limitations by providing increased computational power and allowing parallel execution of different applications within the system. However, the transition from traditional single-core to contemporary multi-core computing platforms is non-trivial and requires a systematic and well-defined migration process. This paper reviews some of the existing migration methods and provides a systematic multi-phase migration process with emphasis on software architecture recovery and transformation to explicitly address the timing and dependability attributes expected of industrial software systems. The methodology was evaluated using a survey-based approach and the results indicate that the presented methodology is feasible, useable and useful for real-time industrial software systems.

Implementation of High Performance EEG Based Seizure Detection And Analysis On Multicore Platform

About 50 million people worldwide suffer from epilepsy, the neurological disorder characterized by seizures. The primary tool for diagnosis of an epileptic seizure is an electroencephalography (EEG) which records the brain’s spontaneous electrical activity. This requires the placement of a minimum of 16 electrodes on the scalp with each electrode being interpreted as a channel. The classification of seizure detection and analysis techniques mainly work in two stages, where features are extracted from raw EEG data in the first stage and then the obtained features are used as input for the classification process in the second stage. Traditionally the Seizure detection algorithms were implemented using DSP Processor or FPGAs. But these single core platforms are constrained with respect to speed of operation and power consumption. There is a greater need to reduce the power consumption as well to increase the speed of EEG seizure detection system. This problem can be addressed using the Multicore Processors, which process data simultaneously. This project presents a high performance multicore platform for EEG based seizure detection and analysis. This platform performs continuous multichannel detection and analysis of seizures for epilepsy patients. The detection unit will detect the seizures based on feature extraction process once the seizure detection is done enables the analysis circuit that process the data based Uridva Triyabhakyam based 128 point FFT and transmits energy and frequency contents of EEG data. All proposed blocks are simulated and synthesized using Xilinx ISE and coding is done in Verilog.

Implementation of High-Performance EEG Based Seizure Detection And Analysis On Multicore Platform

About 50 million people worldwide su?er from epilepsy, the neurological disorder characterized by seizures. The primary tool for diagnosis of an epileptic seizure is an electroencephalography (EEG) which records the brain’s spontaneous electrical activity. This requires the placement of a minimum of 16 electrodes on the scalp with each electrode being interpreted as a channel. The classification of seizure detection and analysis techniques mainly work in two stages , where features are extracted from raw EEG data in the first stage and then the obtained features are used as input for the classification process in the second stage. Traditionally the Seizure detection algorithms were implemented using DSP Processor or FPGAs. But these single core platforms are constrained with respect to speed of operation and power consumption. There is a greater need to reduce the power consumption as well to increase the speed of EEG seizure detection system. This problem can be addressed using the Multicore Processors, which process data simultaneously. This project presents a high performance multicore platform for EEG based seizure detection and analysis. This platform performs continuous multichannel detection and analysis of seizures for epilepsy patients. The detection unit detects seizures based on feature extraction process once seizure detection is done enables the analysis circuit that process the data based Uridva Triyabhakyam based 128 point FFT and transmits energy and frequency contents of EEG data. All proposed blocks are simulated and synthesized using Xilinx ISE and coding is done in Verilog.

Parallel computation of regional CORS network corrections based on ionospheric-free PPP

Global navigation satellite system real-time processing requires low latency, high timeliness, and high computational efficiency. A typical application is providing corrections using data from a regional Continuously Operating Reference Station (CORS) network. Usually the wide-lane and narrow-lane fractional cycle biases (FCBs) are determined at the server and broadcast to users to fix undifferenced ambiguity. Also, a tropospheric model is established at the server and broadcast to users to obtain accurate and reliable a priori zenith total delays for precise point positioning (PPP) using the ionospheric-free (IF) observation combination. Currently, serial methods are typically applied, i.e., all reference stations are involved in estimating the wide-lane and narrow-lane FCBs and establishing a regional tropospheric delay model. To improve the efficiency and shorten the latency, we develop a parallel computation method for regional CORS network corrections based on IF PPP by adopting a multicore parallel computing technology task parallel library, wherein parallel computations involving the FCBs, tropospheric delays, and tropospheric model are successively performed based on data parallelism, in which the same operation is performed concurrently on elements in an array, and task parallelism, which refers to one or more independent tasks running concurrently. Data covering four seasons from the Hong Kong and southwestern America CORS networks are utilized in the experiment. The single differenced FCBs between satellites are determined within each full pass, and a tropospheric model with an internal accuracy better than 1.4 cm and an external accuracy better than 1.6 cm is derived at the server. With the parallel implementation, the speedup ratios of FCB estimation and tropospheric modeling are 1.79, 3.15, 5.59, and 9.69 times higher for dual-core, quad-core, octa-core, and hexadeca-core platforms, respectively, than for a single-core platform.

Research of a resource-efficient, real-time and fault-tolerant wireless sensor network system

Memory optimization, energy conservation, real-time scheduling and fault tolerance are the essential research topics in the wireless sensor network (WSN). In this paper, a memory-efficient, energy-efficient, real-time and fault-tolerant WSN system LiveOS is designed and implemented. Compared to the other systems, LiveOS has several typical features. Firstly, the optimized Rate-Monotonic Scheduling (RMS) scheduling algorithm is implemented. By doing this, the memory cost of the multithreaded real-time operating system (RTOS) can be 47.3% optimized if compared to the traditional single-core node. Consequently, the RTOS becomes appropriate to run even on the memory-constrained WSN nodes. Secondly, the new research approach that addresses the WSN challenges by combining both the multi-core hardware technique and the software technique is applied in LiveOS. By means of the multi-core hardware support, the energy cost of LiveOS can be 35% optimized compared to the traditional single-core platform. Moreover, the real-time scheduling performance and the fault-tolerant ability of the WSN nodes can be optimized significantly. Due to the above features, LiveOS becomes the WSN system which has small memory footprint, long lifetime, high real-time scheduling performance and upstanding fault-tolerant ability. The evaluation on the different prototype nodes proves that LiveOS is appropriate to run on the resource-constrained WSN platforms and is competent to execute the outdoor real-time WSN applications.

Analysis and Design of Computerized Numerical Controls for Execution on Multi-core Systems

Multi-core processors offer a performance increment compared to single-core platforms. This leap in performance is desired to be ported to computerized numerical controls. However, in order to profit of the benefits multi-core processors can bring, the software has to be tailored to real parallel execution. In this paper a concept is proposed for partitioning numerical control software functions for being concurrently executed on multi-core systems. Specifically, the interpreter and the cutter radius compensation modules have been analyzed for devising a feasible parallel architecture. The parser algorithm has been implemented following the proposed scheme in a thread-based approach. Experiments were conducted under a real time Linux kernel extension utilizing the PREEMPT_RT patch. The results were compared against its serial version in terms of execution times to validate the concept.

Enhanced fixed-priority real-time scheduling on multi-core platforms by exploiting task period relationship

One common approach for multi-core partitioned scheduling problem is to transform this problem into a traditional bin-packing problem, with the utilization of a task being the “size” of the object and the utilization bound of a processing core being the “capacity” of the bin. However, this approach ignores the fact that some implicit relations among tasks may significantly affect the feasibility of the tasks allocated to each local core. In this paper, we study the problem of partitioned scheduling of periodic real-time tasks on multi-core platforms under the Rate Monotonic Scheduling (RMS) policy. We present two effective and efficient partitioned scheduling algorithms, i.e. PSER and HAPS, by exploiting the fact that the utilization bound of a task set increases as task periods are closer to harmonic on a single-core platform. We formally prove the schedulability of our partitioned scheduling algorithms. Our extensive experimental results demonstrate that the proposed algorithms can significantly improve the scheduling performance compared with the existing work.

A Heterogeneous Multi-core Architecture with a Hardware Kernel for Control Systems

Rapid industrialisation has resulted in a demand for improved embedded control systems with features such as predictability, high processing performance and low power consumption. Software kernel implementation on a single processor is becoming more difficult to satisfy those constraints. This paper presents a multi-core architecture incorporating a hardware kernel on FPGAs, intended for high performance applications in control engineering domain. First, the hardware kernel is investigated on the basis of a component-based real-time kernel HARTEX (Hard Real-Time Executive for Control Systems). Second, a heterogeneous multi-core architecture is investigated, focusing on its performance in relation to hard real-time constraints and predictable behavior. Third, the hardware implementation of HARTEX is designated to support the heterogeneous multi-core architecture. This hardware kernel has several advantages over a counterpart kernel implemented in software: higher-speed processing capability, parallel computation, and separation between the kernel itself and the applications being run. A microbenchmark has been used to compare the hardware kernel with the software kernel, and compare the kernel on the multi-core platform with the kernel on the single-core platform.

Managing Data-Objects in Dynamically Reconfigurable Caches

The widening gap between processor and memory speeds makes cache an important issue in the computer system design. Compared with work set of programs, cache resource is often rare. Therefore, it is very important for a computer system to use cache efficiently. Toward a dynamically reconfigurable cache proposed recently, DOOC (Data-Object Oriented Cache), this paper proposes a quantitative framework for analyzing the cache requirement of data-objects, which includes cache capacity, block size, associativity and coherence protocol. And a kind of graph coloring algorithm dealing with the competition between data-objects in the DOOC is proposed as well. Finally, we apply our approaches to the compiler management of DOOC. We test our approaches on both a single-core platform and a four-core platform. Compared with the traditional caches, the DOOC in both platforms achieves an average reduction of 44.98% and 49.69% in miss rate respectively. And its performance is very close to the ideal optimal cache.