Single-chip Implementation Research Articles

Pipelined Hardware Implementation of COPA, ELmD, and COLM

Authenticated encryption algorithms offer privacy, authentication, and data integrity, as well. In recent years, they have received special attention after the call for submissions of Competition for Authenticated Encryption: Security, Applicability, and Robustness (CAESAR) was published. The CAESAR goal is to generate a portfolio with recommendations of authenticated encryption algorithms for three different scenarios: Lightweight, high speed, and defense in deep. ELmD and COPA are two on-line authenticated encryption algorithms submitted to CAESAR; because of their similarities, they were merged as COLM during the third-round of CAESAR. COLM is a finalist in the use case 3 defense in depth . ELmD, COPA, and COLM are based on the ECB-mix-ECB structure, which is highly parallelizable and pipelineable. In this paper, we present optimized single-chip implementations of ELmD, COPA, and COLM using pipelining. For ELmD, we present implementations for eight combinations of its parameters set: For intermediate tags, fixed, variable tag length, and 10 and 6 AES rounds. COLM implementation is for variable tag length without intermediate tags. In the case of COPA, it does not have parameters set. The implementation results with a Xilinx Virtex 6 FPGA show that ELmD is the best option concerning area and speed for single-chip implementation. The area of COPA and COLM are 1.65 and 1.69 times ELmD's respectively. Regarding throughput, the range of our implementations goes from 33.34 Gbits/s for COLM to more than 35 Gbits/s for several versions of ELmD.

A New Floating-gate Radiation Sensor and Readout Circuit in Standard Single-Poly 130-nm CMOS Technology

This paper describes a new dosimeter, which is composed of a Floating-Gate-Radiation-Field-Effect-Transistor (FGRADFET) sensor and novel absorbed-dose and a dose-rate readout circuit. It is a single-chip implementation employing a standard single-poly 130-nm CMOS technology. The FGRADFET extends the floating-gate (FG) as an extra silicon-area ( $60\,\,\mu \text{m}\,\,\times 200\,\,\mu \text{m}$ ) of poly-over-field-oxide (FOX) that acts as a catchment to sense the radiation from the environment. There is also a parallel array of 16 pMOS transistors ( $1\,\,\mu \text{m}\,\,\times 2\,\,\mu \text{m}$ each) at the edge of the FOX catchment-area to charge the FG by the Fowler–Nordheim tunneling effect prior to the sensor deployment. Thus, no bias voltage is needed for the FG transistors during the irradiation. A cascode current-mirror, a reference FGRADFET, and 16 reference pMOS transistors are employed to compensate temperature effects and read the FG voltage of the FGRADFET sensor, which is proportional to the total absorbed dose. A further processing circuit for the FG voltage output is also designed to extract the slope of the FG voltage (the dose-rate). These circuits include differentiator, preamplifier buffer, chopper-amplifier, low-pass filter, and double-ended-to-single-ended output amplifier. The measured average sensitivity of around 3.86 mV/rad was achieved for X-ray irradiation. It consumes 320 $\mu \text{W}$ in detecting the dose-rate with a 1–10 rad/min measurement range corresponding to the single-ended output ranging from 220 to 960 mV.

Single-chip Implementation of LVDT Signal Conditioning

The aim of this work was to prove that the signal conditioning electronics for linear variable transformers (LVDTs) can be implemented in inexpensive, general-purpose 8-bit microcontrollers, making expensive dedicated signal conditioning chips redundant. A low-cost, high-resolution signal conditioning solution for LVDTs is presented. Apart from a few external passive components, the entire solution is implemented in a low-cost, analog-digital hybrid microcontroller. The excitation sinusoid is generated by filtering out the fundamental frequency of a (self-sustained) pwm-generated square wave and the secondary coils’ signals are demodulated with classic peak detector circuits implemented in the microcontroller using a combination of its embedded analog and digital building blocks. A resolution of 1 m over a range of ±6.35 mm for a commercial LVDT is reported and an uncertainty of 6 m in the absolute value is deduced. The entire solution is implemented as surface mounted components on a small printed circuit board and the LVDT core displacement is displayed on an LCD display. Due to the simplicity and low-cost components required, this signal conditioning proposal has the potential to have a significant impact on commercial LVDT signal conditioning chips in the future since it is significantly less expensive than the present state-of-the-art signal conditioning chips offered by the main commercial suppliers and other solutions previously suggested in scientific literature.

3D Multilayer Mesh NoC Communication and FPGA Synthesis

Network on chip (NoC) is the latest approach in which multiprocessors are integrated in a single chip and FPGA implementation makes it scalable and reconfigurable. It is the feasible solution for pipelined architecture and parallel processing in multiprocessor system on chip. The research article presents the NoC architecture for flexible and scalable design under 3D mesh topological structure. The design is considered for 8 layers as multilayered architecture. In one layer 64 nodes can communicate with each other. The design is developed with the help of VHDL programming in Xilinx ISE 14.2 software and functionally simulated in Modelsim 10.0 student edition software. The performance of the design is analyzed with hardware parameters and timing utilization parameters on Virtex 5 FPGA. The inter and intra communication among the nodes is verified on the same FPGA. The design is verified on Virtex-5 FPGA with 8, 16, 32, 64 and 128 bit data transfer among nodes when the NoC is fully connected and utilized. The paper also presents the comparative study of the 3D, 8 layer mesh NoC for different cluster size (2 × 2 × 2), (3 × 3 × 3) and (4 × 4 × 4), based on the FPGA synthesis parameters. The scalable architecture is applicable for the nodes communication in a wireless sensor network in which multiple nodes are communicating in defined field and configured in specific topology such as Zigbee standard (IEEE 802.15.4) follow mesh, one of the topology.

C-Band Single-Chip Radar Front-End in AlGaN/GaN Technology

This paper presents the design and measurement results of a single-chip front-end monolithic microwave integrated circuit (MMIC), incorporating a high-power amplifier, transmit–receive switch, low-noise amplifier, and calibration coupler, realized in 0.25 $\mu \text{m}$ AlGaN/GaN-on-SiC MMIC technology of UMS (GH25-10). The MMIC is operating in C-band (5.2–5.6 GHz) and is targeting the next generation spaceborne synthetic aperture radar. The use of GaN technology has resulted in a design that is robust against antenna load variation in transmit as well as against high received power levels, without the need for an additional limiter. By including a transmit-receive switch on the MMIC there is no need for an external circulator, resulting in a significant size and weight reduction of the transmit–receive module. The measured output power in transmit is higher than 40 W with 36% PAE. The receive gain is higher than 31 dB with better than 2.4 dB noise figure. To the best of the author’s knowledge this is the first time such performance has been demonstrated for a single-chip implementation of a C-band transmit–receive front-end.

An Embedded System for a High-Speed Manipulator With Single Time Scale Visual Servoing

This study presents the development of an embedded system for controlling a high-speed robotic manipulator. Three different types of controllers including hardware proportional derivative (PD), software PD, and single time scale visual servoing are considered in this study. Novel field programmable gate array (FPGA) technology was used for implementing the embedded system for faster execution speeds and parallelism. It is comprised of dedicated hardware and software modules for obtaining sensor feedback and control signal (CT) estimation, providing the control signal to the servovalves. A NIOS II virtual soft processor system was configured in the FPGA for implementing functions that are computationally expensive and difficult to implement in hardware. Quadrature decoding, serial peripheral interface (SPI) input and output modules, and control signal estimation in some cases was carried out using the dedicated hardware modules. The experiments show that the proposed controller performed satisfactory control of the end effector position. It performed single time scale visual servoing with control signal updates at 330 Hz to control the end effector trajectory at speeds of up to 0.8 ms−1. The FPGA technology also provided a more compact single chip implementation of the controller.

Реалізація криптографічних алгоритмів на основі ПЛІС для цифрових розподілених систем

This paper presents a single chip efficient FPGA implementation of RSA and DES for Digital Envelope Scheme that targets the Altera Apex 20KE EP20k200EBC356. Implementation of cryptographic algorithms on programmable devices like FPGAs run much faster than on software while preserving physical security of hardware solutions. The high throughput in the implementation of cryptographic algorithms for digital envelope scheme is achieved by means of exploiting the parallelism present in the DES and RSA operations as well as the features of Altera Apex 20KE device family which best suit for system-on-a-programmable-chip (SOPC) applications. The parallelized single chip implementation of DES and RSA for performing the Encryption/Decryption for the Digital envelope scheme offers a throughput of 3.5 Gbits/sec at a system clock rate of 54.7 MHz. This implementation even provides a means for using the DES and RSA separately.

Design and Implementation of a Face Recognition System-on-a-Chip for Wearable/Mobile Applications

This paper describes the design and implementation of a System-on-a-Chip (SoC) for face recognition to use in wearable/mobile products. The design flow starts from the system specification to implementation process on silicon. The entire process is carried out using a FPGA-based prototyping platform environment for design and verification of the target SoC. To ensure that the implemented face recognition SoC satisfies the required performances metrics, time analysis and recognition tests were performed. The motivation behind the work is a single chip implementation of face recognition system for target applications.

Design of a DPSK Modem Using CORDIC Algorithm and Its FPGA Implementation

ABSTRACTIn the present work, a power efficient differential phase shift keying (DPSK) modem has been implemented using COordinate Rotation DIgital Computer (CORDIC) algorithm in hardware descriptive language (VHDL) code. Here, CORDIC algorithms are used to generate the carrier in the modulator and to implement the multiplier in the demodulator. Carrier generator on the same chip minimizes the effect of noise significantly. Single-chip implementation provides a low power DPSK modem operating with high frequency which is suitable for wireless communication system. The CORDIC algorithm based DPSK modem is found to be a much efficient system in terms of reduced hardware cost, improved performance, and included flexibility. Importance of portable field programmable gate array (FPGA) based device for wireless communication system and system on single chip is now growing rapidly. In this context, the proposed modem provides an efficient alternative over conventional DPSK modem. Real-time verification is performed using Kintex-7 FPGA board. The performance of the proposed modem has been compared with a normal DPSK modem implemented in software defined radio kit using Xilinx block and Spartan-6 FPGA.

A V-Band 8$\,\times\,$8 CMOS Butler Matrix MMIC

This paper presents a fully integrated V-band 8 x 8 Butler matrix in 0.13-μm CMOS technology. Since the number of building blocks exponentially increases with the order of the Butler matrix, the constituted components, including quadrature hybrids, phase shifters, and crossovers, must be redesigned for single-chip implementation in silicon. Design equations and novel layout arrangements are described. A demonstrated 8 x 8 Butler matrix was implemented, which has the compact chip size of 1.45 x 0.93 mm2, no dc power consumption, and low average loss of 3.1 dB. Eight spatial beams with the averaged 5.9 dBi gain and 0.6° main-beam direction tolerance were obtained in 56 to 66 GHz.

Microprocessor architecture: from simple pipelines to chip multiprocessors

This book gives a comprehensive description of the architecture of microprocessors from simple in-order short pipeline designs to out-of-order superscalars. It discusses topics such as - the policies and mechanisms needed for out-of-order processing such as register renaming, reservation stations, and reorder buffers - optimizations for high performance such as branch predictors, instruction scheduling, and load-store speculations - design choices and enhancements to tolerate latency in the cache hierarchy of single and multiple processors - state-of-the-art multithreading and multiprocessing emphasizing single chip implementations Topics are presented as conceptual ideas, with metrics to assess the performance impact, if appropriate, and examples of realization. The emphasis is on how things work at a black box and algorithmic level. The author also provides sufficient detail at the register transfer level so that readers can appreciate how design features enhance performance as well as complexity.

Design of a client server application using the Bluetooth protocol

In 1998, five major companies (Ericsson, Nokia, IBM, Toshiba and Intel) formed a group to create a license-free technology for universal wireless connectivity in the handheld market. The result is Bluetooth. The Bluetooth specifications (currently in version 1.1) define a radio frequency (RF) wireless communication interface and the associated set of communication protocols and usage profiles. The link speed, communication range and transmission power level for Bluetooth were chosen to support low-cost, power-efficient, single-chip implementations of the current technology. In fact, Bluetooth is the first attempt at making a single-chip radio that can operate in the 2.4-GHz ISM (industrial, scientific and medical) RF band. While most early Bluetooth solutions are dual-chip, vendors have recently announced a singlechip versions as well. The current study of the Bluetooth technology describes structure, protocol stack, architecture, connectivity, security issues, and finally design a client server application using Java programming language.

AN EFFICIENT DESIGN FOR MOTION-JPEG2000 SYSTEM IN REAL-TIME VIDEO ENCODING

Motion-JPEG2000 is derived from Part 1 of the JPEG2000 standard and provides high quality image compression in video coding system. This paper presents a real-time Motion-JPEG2000 encoding which is built on a fixed-point digital signal processor (DSP) as a single-chip implementation. The design addresses on the system-level design considerations. Among several modules in JPEG2000, Embedded Block Coding with Optimized Truncation (EBCOT) algorithm contains the highest computation complexity and also becomes the bottleneck of JPEG2000. Two speed-improved methods are proposed to significantly reduce the processing time of EBCOT. The fast algorithm is used by processing the three coding passes in sequential and is very suitable to the execution on programming-based processor. For Motion-JPEG2000 implementation, a real-time encoding system is built on the single-chip DSP processor without any extra hardware support. The optimization techniques are also applied to enhance the performance. Due to the contribution on algorithm and implementation issue, the complexity of Motion-JPEG2000 is largely reduced. Simulation results show that the proposed system can process 30 frames per second in CIF size (352 × 288 pixels) with 4:2:0 video sequences. For SDTV size resolution (760 × 480 pixels), the system can achieve near 20 frames per second.

A Speed-Optimized Systolic Array Processor Architecture for Spatio-Temporal 2-D IIR Broadband Beam Filters

For high-speed plane-wave filtering applications, real-time 2-D spatio-temporal linear-array broadband beam filters are required, operating at temporal frame rates in excess of hundreds of megahertz. The corresponding application specific VLSI circuits must have low critical-path latencies. A novel high-speed systolic array architecture for a first-order 2-D broadband frequency-planar spatio-temporal beam filter is proposed for this purpose and employs a field-programmable gate array (FPGA) circuit where the critical path latency is minimized by timing optimization of inter- and intra-parallel processor pipelines, together with 3-D look-ahead techniques. The method facilitates single-chip VLSI circuit implementations operating at real-time frame rates of several hundred megahertz.

Electronic Detection of DNA Hybridization: Toward CMOS Microarrays

Low-cost mass fabrication methods and label-free capacitive biosensors are needed for many applications. This article presents a electronic microarrays, with single-chip implementations in CMOS technology. Although biochemical operations in CMOS-based arrays are almost the same as in optical devices, the simple readout of integrated CMOS sensors greatly facilitates system integration. These chips can perform a significant amount of sensor data processing and produce digital output signals in standardized form. They can be easily connected to simple, inexpensive, handheld or even wearable readers. However, these devices are in their infancy. Only a small subset of them are at the level of complete single-die integration of sensors, transducers, and data-conditioning circuits. Our purpose in this article is to outline the main technology, design, and implementation challenges involved in developing these highly integrated research prototypes.

High-rate CCSDS formatter/encoder plus IDEA encryptor as a single-chip solution

Link data processing systems for advanced satellite applications require high throughput implementations of formatting/encoding as well as of encryption functions. Configurable field programmable gate arrays (FPGA) provide flexible solutions to implement these functions, but their sensitivity to the space radiation environment requires special design provisions. In this article, typical downlink processing functions and throughput demands are addressed. A single-chip implementation including encryption function based on International Data Encryption Algorithm (IDEA) [Media Crypt AG, IDEA Technical Description, www.mediacrypt.com, September 2003] within a configurable FPGA is presented.

A New Control System With a Control Delay Compensation for a Current-Source Active Power Filter

In this paper, a new control system for the current-source active power filter is presented. The harmonic current compensation is realized using combined feedforward control of the load currents and closed-loop control of the supply currents. The control system includes a simple method for compensating the sampling and calculation delays of the digital control system. The compensation in the proposed method is achieved using the regular LC filter of the active power filter as an energy storage for load currents, and no additional components is needed in the main circuit. Furthermore, the calculation power demand of the compensation method is very low and is, therefore, suitable for single-chip microcontroller implementations. The proposed control system is realized using a 32-bit Motorola MPC555 microcontroller. The simulation and experimental results show effective filtering performance also for higher order harmonics of the distorted load currents.

A single-chip storage LSI for home networks

Network direct attached storage (NDAS) is a network storage architecture that allows direct attachment of existing ATA/ATAPI devices to Ethernet without a separate server. Unlike other architectures such as NAS, SAN, and USB mass storage, no server computer intervenes between the storage and the client hosts. We describe an NDAS disk controller (NDC) amenable to low-cost single-chip implementation that processes a simplified L3/L4 protocol and converts commands between ATA/ATAPI and Ethernet, while the remaining complex tasks are performed by remote hosts. Unlike NAS architectures that use TCP/IP, NDAS uses a TCP-like lean protocol that lends itself well to high-performance hardware realization. Thanks to the simple NDAS architecture and protocol, an NDC implemented on a single 4 mm /spl times/ 4 mm chip in 0.18 /spl mu/m CMOS technology achieves a maximum throughput of 55 Mbytes/s on gigabit Ethernet, which is comparable to that of a high-performance disk locally attached to a host computer.

A CMOS Monocycle Pulse Generation Circuit in a Ultra-Wideband Transmitter for Intra/Inter Chip Wireless Interconnection

In this paper we present a simple circuit for generating the monocycle pulses required in a time hopping ultra-wideband transmitter for an intra/inter chip wireless interconnection system. The monocycle pulse, which has a wide bandwidth, is obtained from damped sinusoidal signals generated from a resistance-inductance-capacitance circuit with a low pass resistance-capacitance filter, transmission gate and digital control circuit. A single-chip implementation of this circuit based on 0.18 µm CMOS technology and results of its simulation named “HSPICE” are presented in this paper. The simulation shows that the generated monocycle pulse has wide bandwidth characteristics. The developed circuit consumes low power (4.4 mW) and occupies a small area (0.19 mm2).

System-on-a-Chip Development for Small Satellite Onboard Data Handling

This paper presents research work aimed at miniaturization of the onboard data handling system of a small satellite. A mixed-mode application-specific integrated circuit that represents a single chip implementation of an onboard command and data handling subsystem for a low-cost small satellite is outlined. A system-on-a-chip design of an onboard computer is proposed, which is based on integration of soft intellectual property cores. A downsized onboard computer implementation on a single programmable logic chip and a low-cost communication system are described. Details about the design and integration of a mathematical floating-point co-processor core, based on the CORDIC algorithm, are given. Reconfigurability aspects are discussed.