Single-chip Implementation Research Articles

Fast hardware graphic generators of curve families

Special purpose hardware devices devoted to display families of curves are very attractive when high performance graphic tools are to be designed. In this paper an architecture well suited for fast hardware curve generators is proposed, mainly based on the use of vector generators and ROMs. Curve graphs are approximated by polygonal lines, the extremes of which and a selected subset of vertices can be obtained with the required precision. Output rate is shown to be very close to available vector generators rate. As an example, a device adopting this architecture has been designed for the generation of conic and exponential curves. Precision figures have been obtained in the hypothesis that the generator hardware complexity allows a single chip implementation. The architecture is easily extensible to three-dimensional curves.

Software implementation of floating-point arithmetic on a reduced-instruction-set processor

Current single chip implementations of reduced-instruction-set processors do not support hardware floating-point operations. Instead, floating-point operations have to be provided either by a coprocessor or by software. This paper discusses issues arising from a software implementation of floating-point arithmetic for the MIPS processor, an experimental VLSI architecture. Measurements indicate that an acceptable level of performance is achieved, but this approach is no substitute for a hardware accelerator if higher-precision results are required. This paper includes instruction profiles for the basic floating-point operations and evaluates the usefulness of some aspects of the instruction set.

Single chip implementation of the Levinson algorithm

The design, implementation, and testing procedure are presented for a single chip implementation of the Levinson algorithm. This algorithm provides an iterative procedure for the solution of certain systems of linear equations and is used in many basic problems in communications and signal processing. This chip consists of a 1200-bit RAM memory, a divider based on the nonrestoring division algorithm, a recorder-based multiplier suitable for pipelined operations, and a controller that consists of two PLAs and six address registers. Modifications of the algorithm permit the parallel use of both the multiplier and the divider. The design is done in 4-/spl mu/m NMOS technology, and 12-bit-long operants in two's complement are used. By using a 5-MHz two-phase clock, the chip can compute 20 iterations of the algorithm in approximately 675 /spl mu/s. Application to lattice filtering in linear data channel equilization is considered. Off-line testing of the chip can be done effectively with minimum additional hardware through separate data and control buses.

Single-Chip Implementation of Feature Measurement for LPC-Based Speech Recognition

A single-chip implementation of Linear Predictive Coding (LPC)-based feature measurement for speech recognition, called the Feature Extracting Digital Signal Processor (FXDSP), has been developed by programming the AT&T DSP20™ programmable Digital Signal Processor (DSP) and has been verified by both numerical simulation and system use. For identical input, the recognition distance between floating point simulation and the DSP implementation was found to be negligibly small when compared with distances for word matches. The feature-measurement technique is identical to that used in numerical simulations of LPC-based isolated- and connected-word recognition using combinations of dynamic time warping, vector quantization, and hidden Markov modeling. As a result, the FXDSP represents a single-chip common building block for real-time implementation of most speech recognition techniques under investigation at AT&T Bell Laboratories. The FXDSP performs eighth-order LPC analysis on speech received from a standard CODEC. In every frame period (15 ms) it produces a feature vector consisting of the log energy, nine amplitude-normalized autocorrelation coefficients, and nine LPC-based test-pattern coefficients. The feature-measurement program requires 1023 locations of the 1024 available in on-chip program ROM, 211 of 256 available RAM locations, and 75 percent of available real time.

A bit-serial architecture for digital signal processing

This paper describes the architecture of a bit-serial VLSI circuit designed for digital signal processing applications. This circuit is capable of performing matrix-vector multiplications in a totally pipeline fashion. Although this circuit naturally performs multiplication of a 3 \times 3 matrix with a 3-element vector at a time, it can perform a (matrix) \times (vector) operation of any size. Under different control modes, the same architecture can also perform vector addition and scalar multiplication of vectors of arbitrary length. The circuit has been designed for a single chip implementation using 4 \mu -NMOS technology. The word size of the chip is 16 bits, and the data is provided in 2's complement form. The chip contains approximately 6000 transistors in an area of 5.7 {mm}^{2} and operates with a 6-MHz two-phase clock in direct interface with a 6-MHz microprocessor. It can also be interfaced with a programmable digital signal processor. The chip is housed in a 64-pin DIP. A self-testing scheme incorporated into the design allows fault detection and isolation in a particular unit (storage or arithmetic unit) during the data processing.

VLSI Processor Architecture

A processor architecture attempts to compromise between the needs of programs hosted on the architecture and the performance attainable in implementing the architecture. The needs of programs are most accurately reflected by the dynamic use of the instruction set as the target for a high level language compiler. In VLSI, the issue of implementation of an instruction set architecture is significant in determining the features of the architecture. Recent processor architectures have focused on two major trends: large microcoded instruction sets and simplified, or reduced, instruction sets. The attractiveness of these two approaches is affected by the choice of a single-chip implementation. The two different styles require different tradeoffs to attain an implementation in silicon with a reasonable area. The two styles consume the chip area for different purposes, thus achieving performance by different strategies. In a VLSI implementation of an architecture, many problems can arise from the base technology and its limitations. Although circuit design techniques can help alleviate many of these problems, the architects must be aware of these limitations and understand their implications at the instruction set level.

One-pass, speaker-independent, isolated digit recognition system

The system described in this paper is an outgrowth of one presented earlier [J. Acoust. Soc. Am. Suppl. 1 72, S30 (1982)]. It is a combination of deterministic and probabilistic approaches to isolated word recognition. The most distinguishing features of the new system are a real-time, one-pass algorithm and the use of telephone-quality speech rather than broadband microphone speech. This new version is targeted to a single chip implementation with the requirement that the system uses no more than 256 bytes of RAM and 8000 bytes of ROM. The system makes decisions based on a single 20 ms frame often features (with no long term storage of previous frames). Preliminary segmentation and matching are combined to significantly reduce both the number of confusable words at each recognition point as well as the memory requirement for references obtained during the multispeaker training. The system was evaluated on a ten digit vocabulary (1000 tokens, 21 talkers) and showed an accuracy of 94.4% with a 3.1% error rate, and a 2.5% rejection rate. The effects of using a one-pass algorithm on total performance are also discussed.

Novel architecture for a time division switch

A layout for a single-chip implementation of a time switch for a digital switching system is described. Using only a few simple cell types, a complete switch can be designed by connecting the cells in regular arrays. Interconnect wiring is incorporated into the cells, so the effort required to design a time switch of any size is minimised.

Digital Filtering Using the Intel 2920 Signal Processor

The concepts of single-chip digital Filter implementation are presented via a student-oriented tutorial/laboratory case study. This involves the design of lowpass, highpass, bandpass and bandstop digital filters using the bilinear z-transform method. Concurrent implementation of the Filters using the Intel 2920 single-chip signal processor is described.