Single-chip Digital Signal Processor Research Articles

An Advanced Robot Control System Using a DSP-Based Vector Computation Engine

In this paper, explanations for the configuration and usage of a vector computation engine designed to meet the growing demand for higher-speed operation, more precise robotics and real-time motion simulation are given. Presented is an example of its application to a robot controller making full use of high operational performance. This engine is a floating-point vector processor based on a single-chip digital signal processor (μPD77230) with vector matrix and various functions such as a trigonometrical function, data transfer functions-- being built into an internal instruction memory. In this engine, a multiplication of 4 × 4 element transformation matrices can be done in less than 30pseconds. Active stiffness control operation (involving force control in addition to position control) in less than 0.7 milliseconds. In other words, this single-chip engine makes it possible to achieve high-level control comparable to a minicomputer, thus providing a compact, light and inexpensive robot controller.

A hardware implementation of an autoregressive algorithm

With short length data records, high-resolution spectral estimates can be obtained by constructing a model of the signal and using the model coefficients to calculate the spectrum. The bottlenecks associated with implementing modelling algorithms in hardware were identified using a test bed based on a general-purpose microprocessor. A comparison is made of the architecture required and speed obtained when the Burg autoregressive modelling algorithm is implemented on high-speed multiprocessor systems. The systems compared were the microprogrammable AMD29500 byte slice digital signal processor chips and the NEC mu PD77230 single-chip digital signal processor. Applications in the area of magnetic resonance imaging are discussed. Prototype systems would allow a sixteenth-order autoregressive model to be performed on a 256*128 medical image in 1 to 3 seconds.

Hands‐free telephone using compact echo cancelers and voice‐switched attenuators

An all‐in‐one type hands‐free telephone set was constructed by using a single chip digital signal processor integrated circuit (DSP IC). It includes a compact acoustic echo canceler, a sidetone echo canceler, and voice‐swilched variable attenuators. An echo canceler whose length is only 16 ms (128 taps for an 8‐kHz sampling) can suppress the power of an impulse response of the loudspeaker‐microphone acoustic coupling path by more than 15 dB, because the major part of the path for an all‐in‐one telephone set is due to short direct paths. Most of the sidetone can also be suppressed by more than 20 dB by using an echo canceler of 8‐ms length. A speech circuit including these echo cancelers and conventional voice‐switched variable attenuators was composed of only one medium‐performance DSP IC (75‐ns machine cycle, 2K words of ROM and 512 words of RAM, and an additional 1000 ASIC gates}, CODEC IC's, and a few analog IC's. Complete simultaneous conversation is feasible with this hands‐free telephone circuit because the voice‐switched attenuation could be reduced to 10 dB or less.

Evaluation of real time adaptive noise cancelling algorithms as implemented using a digital signal processor chip

Adaptive lattice noise cancelling algorithms have features that make them appear attractive for the realisation of realtime adaptive noise cancellers with single chip digital signal processors. Two popular adaptive lattice noise cancelling algorithms have been evaluated for this application. Considered are stochastic gradient lattice and least squares lattice algorithms. For the purpose of comparison, the stochastic gradient transversal algorithm is also evaluated. Their performances under a variety of signal and noise excitations are summarised and compared in terms of operating rates and misadjustments.

A DSP-based adaptive controller for a smooth positioning system

The implementation of a self-tuning regulator for the positioning of a direct-drive servomotor is described. The servo motor is a permanent magnet DC motor in which no speed reducer is used. The auto-tuning regulator consists of two major loops. The inner loop contains a feedback (PD or PID) regulator with additional feedforward terms. The parameters of the feedforward compensation are adjusted by the outer loop, which contains an online parameter estimator. The estimator is based on a recursive least-squares equation, and the estimated parameters are the load inertia and viscous friction. This self-tuning regulator has been simulated with PC.MATLAB, and the results demonstrate the high performance of the scheme. Experimental results obtained with a small DC motor (Electrocraft E-576) are presented, and these results show good agreement with the digital simulation results. There are two innovative aspects to this work. First, parameter estimation is used to adapt the feedforward compensation terms instead of the gains of the feedback controller, as usually is the case in conventional indirect self-tuning regulators. Secondly, the complete adaptive controller has been implemented using a single-chip digital signal processor (DSP), which results in the reduction of system hardware and cost.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Directions in DSP processors

The evolution of single-chip digital signal-processor (DSP) architectures is discussed. It is argued that multiple arithmetic units and functionally enhanced arithmetic units are promising directions for further evolution of the datapath architecture. Candidate structures are defined, and the operation of popular DSP benchmarks on these structures is demonstrated.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Power normalized update algorithm for adaptive filters-without divisions

Two power-normalized update algorithms for adaptive filters are described that do not require divisions. The algorithms are based on very simple iterative procedures that approximate divisions. Since neither the quotients nor the dividends change quickly, the division procedures need only be updated once each time the coefficients of the adaptive filter are updated. One algorithm requires three extra multiplications per coefficient and results in adaptive filters with convergence times practically identical to those achieved when actual divisions are used. The second algorithm requires only one multiplication per coefficient instead of a division, yet results in adaptive filter convergence times only slightly larger than those obtained with real divisions. Both algorithms result in adaptive filters only slightly more complex than steepest descent adaptive filters. The algorithms are especially applicable to real-time adaptive filters realized using single-chip digital signal processors or custom ASICs where hard-wired dividers are usually not available and fast convergence is still desired. >

Impact of digital signal processing on measurement and test instruments

The authors discuss the impact of digital signal processing on test instruments and describe the use of a single-chip digital signal processor called TriStar whose architecture has been tailored for the instrumentation environment. TriStar instructions and programming are described, and attention is given to typical applications of TriStar, including averaging, fast Fourier transform, and interpolations. The authors explain how the processor delivers high throughput for these applications.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Practical implementations off block-mode image filters using the fermat number transform on a microprocessor-based system

The paper investigates the practical aspects of using the Fermat number transform (FNT) as a block-mode image filtering tool on small microprocessor-based systems, which appears not to have been reported previously. This includes the use of state-of-the-art technology such as fully customised VLSI, gate array and single-chip digital signal processors for the implementations of the various FNT-related hardware. The problems encountered in the image filter implementation, owing to the special feature of the FNT, have been carefully studied and solutions proposed which would enable these to be overcome. Finally, the filter speed performance and the feasibility of using the FNT in such an imagefiltering scheme are evaluated.

A Monolithic Integrated Digital Signal Processor for Hifi Audio Applications

The following text describes a new programmable singlechip digital signal processor for top-of-the-range digital audio applications whose architecture and features fulfil exacting requirements. The new digital signal processor (DSP) has been developed for hifi digital audio systems with an analog interface IC (AIC). It is fabricated in 2 micron CMOS technology, and a bond-out version is also available for development purposes.

Design alternatives for adaptive digital lattice filters and a new bit-serial architecture

The problem of the efficient realization of an adaptive digital linear prediction filter is investigated, and three implementation approaches are examined: a single-chip general-purpose digital signal processor realization, a multi-chip, multiplexed architecture, and a multichip systolic array approach. In addition, the complete architecture and organization of a systolic-type realization is also presented. A single-chip lattice stage of the systolic architecture contains both the filtering section and the adaptation logic which is based on the stochastic gradient adaptation algorithm. The filter-stage architecture uses bit-serial arithmetic by employing five bit-serial multipliers and four single-bit adders integrated on a single chip. Chips can be cascaded to obtain multiple-stage filters. The filter architecture is designed to operate with 17-bit, two's complement, fixed-point data with 16-bit precision. At an estimated 8.5-MHz clock rate, the chip could accommodate applications with data sampling rates of 500 KHz.

A 2-/spl mu/m CMOS 10-MHz Microprogrammable Signal Processing Core With an On-Chip Multiport Memory Bank

In this paper a 2-/spl mu/m CMOS, microprogrammable Signal Processor Core (SPC) is described,intended as the number crunching unit in single-chip general purpose digital signal processors. This core contains a 16 X 16 bit paralleI multiplier, a 40-bit multiprecision accumulator, a 40--32-bit extractor, an overflow detection unit, a format adjuster, and a three-port register file for local storage of 15 operands. Its 100-ns throughput rate makes it highly suitable for signal processing systems with sample rates up to 50 kHz (speech, telecom, and HiFi audio). The architecture of this unit is discussed in detail.The design approach, using full-custom cells, bit-sliced functional blocks, and a complete bottom-up logical verification of mask data, is also discribed. The Signal Processor Core contains 19 200 transistors on a 15.5-mm/sup 2/ area. This compares with a packing density of 1200 transistors/mm/sup 2/.

Digital filtering using the NEC μPD7720 signal processor

The concepts of digital filtering using the NEC μPD7720 single-chip digital signal processor are presented. The architecture and instruction formats of the device are summarised. The design philosophy and practical hardware and software considerations of using the 7720 as a peripheral to a host 8085 microprocessor system are discussed.

CMOS single-chip digital signal processor

The HSP (HD61810) is a single-chip digital signal processor which includes a high speed arithmetic logic unit, a high speed multiplier, and a large memory on a single silicon chip. Its architecture features floating point arithmetic and a pipeline structure. With the floating point arithmetic operation, the HSP can manipulate a wide dynamic range of data. The instruction cycle of the HSP is 250 ns. One multiply/add operation can be executed per cycle. The HSP uses 3 μm CMOS technology and so achieves low power consumption. It is programmed by an internal instruction ROM.

A Single Chip Digital Signal Processor and Its Application to Real-Time Speech Analysis

A single chip high-performance digital signal processor (HSP) has been developed for speech, telecommunication, and other applications. The HSP uses 3 µm CMOS technology and its architecture features floating point arithmetic and pipeline structure. By adoption of floating point arithmetic, data covering a wide dynamic range (up to 32 bits) can be manipulated. The input clock frequency is 16 MHz, and the instruction cycle time is 250 ns. Efficient signal processing instructions and a large internal memory (program ROM: 512 words; data RAM: 200 words; data ROM: 128 words) make it possible to construct a compact speech analysis circuit by the LPC (PARCOR) method with two HSP's. This paper describes HSP architecture, LSI design, and a speech analysis application.

A single chip digital signal processor and its application to real-time speech analysis

A single chip high-performance digital signal processor (HSP) has been developed for speech, telecommunication, and other applications. The HSP uses 3 μm CMOS technology and its architecture features floating point arithmetic and pipeline structure. By adoption of floating point arithmetic, data covering a wide dynamic range (up to 32 bits) can be manipulated. The input clock frequency is 16 MHz, and the instruction cycle time is 250 ns. Efficient signal processing instructions and a large internal memory (program ROM: 512 words; data RAM: 200 words; data ROM: 128 words) make it possible to construct a compact speech analysis circuit by the LPC (PARCOR) method with two HSP's. This paper describes HSP architecture, LSI design, and a speech analysis application.

A single-chip digital signal processor for telecommunication applications : Takao Nishitani, Rikio Maruta, Yuichi Kawakami and Hideto Goto. IEEE J. Solid-St. CircuitsSC-16 (4), 372 (1981)

A single-chip digital signal processor for telecommunication applications : Takao Nishitani, Rikio Maruta, Yuichi Kawakami and Hideto Goto. IEEE J. Solid-St. CircuitsSC-16 (4), 372 (1981)

Digital Signal Processor: Tone Generation

Two programs have been written for the recently developed single-chip digital signal processor (DSP) integrated circuit that enable it to function as a tone generator in testing transmission systems. One program is based on the table look-up method and the other on the Maclaurin expansion method. A DSP tone generator based on the look-up method can generate up to 12 components and is suitable for all transmission testing applications. A generator based on the Maclaurin expansion method is limited to less than four components and is particularly applicable in two-tone testing.

A single-chip digital signal processor for telecommunication applications

A single-chip, software-programmable digital signal processor, intended for telecommunication applications, has been developed. The processor, fabricated with the most advanced 3 /spl mu/m n-channel E/D MOS technology, incorporates a 16/spl times/16-bit full hardware multiplier and a sophisticated bus structure to minimize bus conflicts, thus attaining the capability to implement 55 second-order filters at a sampling rate of 8 kHz with sufficient dynamic range to process PCM encoded signals. The authors describe the design concept, architecture, instructions, device design, and application techniques.

Modern dynamo electric machinery

This paper presents techniques for design and control of a brushless direct-current (DC) limited-angle torque motor (LATM) with its application to fuel control of gas turbine engines. Given the desired specifications, a two-pole brushless DC LATM with a toroidally wound armature is designed using selected ferromagnetic material and rare-earth permanent magnets; its electromagnetic characteristics is then computationally found and well tuned using the finite element method (FEM) in order to ensure whether the design meets the performance specifications. To achieve the simple and inexpensive semi-closed-loop fuel control, a robust position controller (including a proportional-integral-derivative (PID) controller with a prefilter) is synthesized for providing the required positioning performance for the developed motor, thereby achieving an inexpensive semi-closed-loop fuel control. A closed-loop fuel controller associated with the proposed position controller and a flow meter is then proposed based on multi-loop control structure in order to achieve required linear input–output relationship. All the proposed fuel control laws were implemented using a stand-alone single-chip digital signal processor (DSP). Experimental results are conducted to show the efficacy and usefulness of the developed limited-angle torque motor with its application to an experimental gas turbine fuel control test platform.