Single Amplifier Biquad Research Articles

A 4th-Order 4-Bit Continuous-Time ΔΣ ADC Based on Active–Passive Integrators With a Resistance Feedback DAC

This article reports a fourth-order continuous-time (CT) delta–sigma modulator (DSM) that features a single-amplifier biquad, a passive integrator, and an active integrator. This simplifies the circuit to only two op-amps in comparison to four power-hungry op-amps used in a conventional fourth-order DSM. In addition to improving the power consumption, the proposed design also has more relaxed requirements for the gain–bandwidth product and the loop gain. A 4-bit flash analog-to-digital converter (ADC) and two feedback digital-to-analog converters (DACs) are employed in this design to implement a fully integrated CT DSM. By incorporating the passive network in front of the last active integrator, this design gives a better attenuation at high frequency, which decreases the possibility of instability caused by out-of-band high-frequency signals. The proposed design has a measured bandwidth of 2 MHz with a power consumption of only around 3 mW. The effective number of bits (ENOB) of the proposed CT-DSM is approximately 12.7 bits with a peak signal-to-noise and distortion ratio (SNDR) around 78 dB, and it also exhibits a good Schreier figure of merit on the order of 166 dB compared to the existing state of the art.

A Single-Opamp Third Order CT ΔΣ Modulator With SAB-ELD-Merged Integrator and Three-Stage Hybrid Compensation Opamp

This paper proposes a 3 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">rd</sup> order continuous-time delta-sigma modulator (CTDSM) with a single amplifier biquad (SAB) and excess loop delay (ELD) merged integrator. The integrator enables a 2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">nd</sup> order noise-shaping together with ELD compensation with just a single Opamp and feedback DAC. A three-stage Opamp with a hybrid frequency-compensation scheme is presented, which achieves high gain and large unity-gain bandwidth (UGBW) with low power. The circuit secures an extra order noise-shaping through a passive noise-shaping SAR (NS-SAR) quantizer (QTZ) while further incorporating a preliminary sampling and quantization (PSQ) technique, the 1 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">st</sup> order NS QTZ can run at 1.5 GHz with 6b. The design, implemented in 28 nm, obtains 74.4 dB SNDR with 50 MHz bandwidth while consuming 10.4 mW from 1.5 V and 1 V power supplies. The prototype attains a dynamic range of 80.6 dB with a Schreier FOM of 171.2 dB. With the presented integrator and Opamp, the loop filter only consumes 14 % of the total DSM power consumption.

A 72.4-dB SNDR 92-dB SFDR Blocker Tolerant CT $\Delta\Sigma$ Modulator With Inherent DWA

This brief presents the design and implementation of a new blocker tolerant wideband continuous-time delta-sigma modulator. Using a customized digital integrator with inherent data-weighted averaging at the back-end of the modulator, the power consumption of the quantizer is reduced while the speed of operation is increased. Additionally, by using a single amplifier biquad structure in the loop filter, the number of op-amps is reduced, thus reducing the analog power consumption. Also, the modulator robustness to the out-of-band blocker is improved by increasing the number of levels in the digital integrator and feedback DACs. The out-of-band blocker tolerance is improved by 3 dB compared to a conventional CIFF-B delta-sigma modulator with a minimal increase in the power consumption. The proposed architecture has been implemented in a 65-nm CMOS technology and operates at a 250 MHz sampling frequency. It achieves 73.5 dB SNR, 72.4 dB SNDR, and 92 dB SFDR over a 7-MHz bandwidth and a Walden figure-of-merit of 341 fJ/conversion.

A 5.35-mW 10-MHz Single-Opamp Third-Order CT &lt;inline-formula&gt; &lt;tex-math notation="LaTeX"&gt;$\Delta\Sigma$ &lt;/tex-math&gt; &lt;/inline-formula&gt; Modulator With CTC Amplifier and Adaptive Latch DAC Driver in 65-nm CMOS

This paper reports a continuous-time (CT) third-order delta-sigma modulator that features a single amplifier biquad (SAB) and a passive integrator to simplify the circuit to just one power hungry operation amplifier (opamp). Such setup not only relaxes the gain and bandwidth requirement of the opamp design but also enhances the overall modulator stability which enables a power-efficient loop filter implementation. We used an SAR architecture in the quantizer with an advanced feedback technique to alleviate its speed penalty. By incorporating the proposed CT complementary (CTC) opamp and an adaptive latch scheme in the DAC driver, the modulator attains a signal bandwidth of 10 MHz with 79.6-dB signal-to-noise and distortion ratio (SNDR) while only consuming 5.35 mW from 1.2- and 1.8-V power supplies. The prototype has a dynamic range of 84.5 dB and a Schreier FoM of 177.2 dB with an active area of 0.033 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .

A Continuous-Time Delta-Sigma Modulator Using ELD-Compensation-Embedded SAB and DWA-Inherent Time-Domain Quantizer

This paper presents an energy-efficient third-order 3 bit continuous-time delta-sigma modulator (CTDSM). In this work, several architectural and circuit techniques are adopted to facilitate a low-power modulator. In the loop filter design, a single-amplifier biquad (SAB) topology is incorporated to realize the desired transfer function. With the SAB architecture, only two amplifiers are needed for implementing a third-order CTDSM. Furthermore, in the proposed SAB, the excess-loop-delay (ELD) compensation is implemented without using an extra summing circuit. For the 3 bit quantizer, a time-domain quantizer is proposed, where the data-weighted-averaging function is embedded in this quantizer to mitigate the nonlinearity issue due to the mismatch of digital-to-analog converter (DAC) unit cells. Fabricated in a 90 nm CMOS technology and clocked at 300 MHz sampling frequency, the proposed SAB-based modulator achieves a 67.2 dB SNDR and a 69.3 dB SNR in an 8.5 MHz signal bandwidth. The overall CTDSM dissipates 4.3 mW and achieves a figure-of-merit of 135 fJ/conversion-step.

On the dynamics of single amplifier biquad based inductor-free hyperchaotic oscillators: a case study

We investigate the dynamics of an inductor-free hyperchaotic oscillator introduced by Giannakopoulos and Deliayannis (Int J Electron 92:143–159, 2005). This oscillator is constructed by coupling an LC oscillator to the Deliyannis single amplifier biquad, which has been turned into an oscillator, by means of a semiconductor diode. Based on the Shockley exponential diode equation, we propose a smooth mathematical model for a better description of both the regular and chaotic dynamics of the hyperchaos generator. Various bifurcation diagrams and corresponding graphs of Lyapunov exponents are plotted to summarize different transitions to chaos/hyperchaos. One of the most striking and interesting finding of this work is the existence of two completely different families of solutions/attractors (depending on the choice of circuit parameters’ values) related to the classical period-doubling route to chaos or to the torus breakdown transition to chaos (which finally gives rise to a hyperchaotic attractor) when monitoring a single circuit component (i.e. the negative resistor). The physical implementation of the oscillator is considered to validate the theoretical analysis through several comparisons between experimental and numerical results. The results of present investigations may be exploited for rigorous designs of such types of oscillators in various engineering applications as well as for educational purposes.

An 80-dB DR, 7.2-MHz Bandwidth Single Opamp Biquad Based CT $\Delta \Sigma$ Modulator Dissipating 13.7-mW

A novel low power compact loop filter using a single amplifier biquad (SAB) network is presented for continuous-time (CT) delta-sigma (ΔΣ) modulators. This new technique reduces power consumption and die area by minimizing the number of active elements and simplifying the modulator topology. The new SAB network has a transfer function (TF) zero, which implements a local feedforward (FF) path in system-level diagram. By having a local FF branch embedded in the SAB network, the FF branches to the summing block in the SAB based feedforward modulator topology is reduced to half the number of FF branches in the conventional topology. Consequently, the SAB based modulator utilizes a switch-capacitor (SC) adder replacing the commonly used CT adder and the sample & hold blocks in the conventional architecture. The SAB based loop filter with reduced FF branches simplifies the design and implementation of the high-order continuous-time ΔΣ modulator. The proposed loop filter is a general filter, which can be used for both high and low oversampling ratios (OSRs). A 4th-order low pass continuous-time ΔΣ modulator is designed and implemented in 130 nm process to confirm the effectiveness of the proposed techniques. Within a 7.2 MHz signal bandwidth, the measured dynamic range and SFDR of this prototype IC are 80 dB and 83.1 dB, respectively, and the total power consumption of 13.7 mW.

Chaotic electronic oscillator from single amplifier biquad

The present letter reports a simple chaotic electronic oscillator. A single amplifier biquad (SAB) based active high-Q Band Pass Filter (BPF) is converted into a chaotic oscillator by introducing a single passive nonlinear element in the form of a general purpose pn junction diode, and a storage element in the form of an inductor. The chaotic circuit is mathematically modeled, which is a set of four coupled first-order autonomous nonlinear differential equations. The behavior of the proposed circuit is investigated through numerical simulations and electronic hardware experiments. It is found that the circuit shows complex behaviors, like, bifurcations and chaos, for a certain range of circuit parameters. The chaotic behavior of the circuit is ensured qualitatively by bifurcation diagram, phase plane plot and experimentally obtained power spectrum, and quantitatively by Lyapunov exponents and Kaplan–York dimensions.

Single amplifier biquad based inductor-free Chua’s circuit

The present paper reports an inductor-free realization of Chua’s circuit, which is designed by suitably cascading a single amplifier biquad based active band pass filter with a Chua’s diode. The system has been mathematically modeled with three-coupled first-order autonomous nonlinear differential equations. It has been shown through numerical simulations of the mathematical model and hardware experiments that the circuit emulates the behaviors of a classical Chua’s circuit, e.g., fixed point behavior, limit cycle oscillation, period doubling cascade, chaotic spiral attractors, chaotic double scrolls and boundary crisis. The occurrence of chaotic oscillation has been established through experimental power spectrum, and quantified with the dynamical measure like Lyapunov exponents.

Single amplifier biquad based autonomous electronic oscillators for chaos generation

Two simple autonomous chaotic electronic circuits have been proposed in this paper. The core of each of the circuits consists of a single amplifier biquad (SAB). We have proposed two configurations of converting this SAB into chaotic oscillators using suitable passive nonlinear element and a storage element in the form of an inductor. The mathematical models of the proposed chaotic circuits have been constructed, which are fourth order autonomous nonlinear differential equations. The behavior of the proposed circuits has been investigated through numerical simulations, Spice-based circuit simulations and electronic hardware experiments and they agree well with each other. It has been found that both the circuits show complex behaviors like bifurcations and chaos for a certain range of circuit parameters.

Single Amplifier Bi-Quadratic Filter Topologies in Transimpedance Configuration

Active-RC configurations, implemented as cascaded bi-quadratic sections (biquads), are the filters of choice for low distortion applications in the base-band. For low power and area applications, single amplifier biquads are best, and are well studied in literature. However, in many applications the input signal is in current domain while the output is a voltage. Output of a current steering digital-analog converter, and output of a down-conversion mixer, are two such examples. In this paper, the authors propose two generic classes of single amplifier bi-quadratic low-pass filter topologies, achieving a second order roll-off in transimpedance (-to-) configuration. Both these topologies are derived with the constraint of fully differential signal processing. The transimpedance active-RC configurations presented here eliminate redundant current-voltage-current conversion and hence provide immense advantages in terms of noise and linearity.

A comparison of five methods for studying a hyperchaotic circuit

A hyperchaotic oscillator based on an LC oscillator and the Deliyannis single amplifier biquad (SAB), coupled by means of a diode, is studied. The inductor of the resonant circuit is realized in practice by using a generalized impedance converter (GIC). Various methods for detecting chaos, such as the Lyapunov exponents, the Lyapunov dimension, the Poincaré map, the spectrum and the phase portraits, are used, in order to confirm the chaotic behaviour of the chaotic circuit. Experimental results fully coincide with theoretical and simulation results. The paper also attempts to answer the question ‘which of the above methods is the most preferable, and why?'. It is concluded that the Lyapunov exponents, Lyapunov dimension and Poincaré map constitute the more reliable methods of confirming chaos.

Lowpass and bandpass transadmittance filter using operational amplifier pole

A new topology simultaneously implementing lowpass (LP) and bandpass (BP) transadmittance filtering signals using a single operational amplifier (OA), one capacitor, and two resistors is presented. The input impedance is very high which is essential for cascading without employment of buffers. The circuit uses absolute minimum number of active and passive components. The filter employs pole-model of OA and as such has acquired suitability for extended frequency operation. The circuit permits separate adjustment of natural frequency ( ω 0 ) and quality factor ( Q) in an orthogonal manner. The circuit has low sensitivity figures unlike the reported single amplifier biquads. The PSPICE simulation results are included.

Active-MOSFET-C single-amplifier biquadratic filters for video frequencies

The authors show how continuous-time active-RC filters can be implemented in CMOS by replacing all resistors by MOSFETs operating in the linear region. As an example, a 24 MHz active MOSFET-C single-amplifier biquadratic lowpass filter with a pole-Q of 3 implemented in a 0.6 /spl mu/m CMOS process is discussed. By comparing measurements of a test chip, simulations and calculations, the following conclusion is reached. As long as the specifications for frequency, pole-Q, spurious-free dynamic range and supply voltage lie within certain limits, then active-MOSFET-C single-amplifier biquads (MOSFET-C SABs) are preferable; with respect to chip size and power consumption, compared to multi-amplifier biquads, e.g. integrator-connected biquads. Above these limits, the latter must be used.

A classification of current-mode single-amplifier biquads based on a voltage-to-current transformation

Using a simple and well-known voltage-to-current transformation, current-mode active RC filters that are amenable to IC realization can be derived from their voltage-based counterparts. Using this transformation, a classification of current-based single-amplifier biquads is introduced which is derived from a similar voltage-based classification. This classification is exhaustive in that it includes all possible current-based single-amplifier biquads.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A comparison of two actively compensated active-RC filters

A number of authors have proposed the use of additional operational amplifiers (op amps) for compensating the detrimental effects of the frequency-dependent gains of the op amps already used in the circuit. This technique is known as active compensation. Among all such actively compensated circuits, two such circuits have been derived from the single amplifier biquad (SAB) of Deliyannis-Friend. These two circuits possess very low passive and active sensitivities. The purpose of this work is to compare their performances not only with respect to the active sensitivities but also from the point of requiring matched op amps and their stability. >

Design of third-order notch RC-active filter sections

Two third-order RC-active filter sections with finite transmission zeros, derived from two commonly used single-amplifier biquads, are examined, and a simple iterative procedure for their design is described, which preserves the low-sensitivity performances of the embedded biquads. Next, the third-order notch section proposed by Boctor is considered and a criterion for its low-sensitivity design is given. Finally, the above mentioned sections together with that recently proposed by Rollett are compared from a sensitivity point of view.

Two-amplifier active-RC biquads with minimized dependence on op-amp parameters

It is generally recognized that the best two-amplifier active- <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">RC</tex> biquads show a better performance with lower sensitivities than single-amplifier biquads (SAB's), and that the performance of an SAB can be improved by use of a composite amplifier. In this paper it is demonstrated that by matching the characteristics of a composite amplifier to the specific filter's requirements a "composite single-amplifier biquad" (CAB) can be obtained with significantly better performance than that of the best two-amplifier biquads reported to date. The resulting circuits are shown by theory and experiment to belong to the best available active- <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">RC</tex> filters.

Parasitic Insensitive, Biphase Switched Capacitor Filters Realized With One Operational Amplifier Per Pole Pair

Practical techniques are given for reducing the number of operational amplifiers (op-amps) in switched capacitor filters. Op-amp count is typically reduced to one op-amp per pole pair, while maintaining the insensitivity to top and bottom plate parasitics heretofore associated with one-op-amp-per-pole structures. These techniques are used to develop a parasitic insensitive single amplifier resonator and a general single amplifier biquad. Next, complete design procedures are given for these circuits. Finally, the same methods are applied to leapfrog structures, where similar op-amp savings are demonstrated.

Active sensitivity minimization in SAB's with active compensation and optimization

In this paper, a new high-gain three-port operational amplifier (OA) circuit is used to replace the single OA in single amplifier biquads (SAB's). The resultant biquads will have the first-order effect of the OA's finite gain-bandwidth products (GB) completely eliminated from their dominant pole frequencies. Then, the widely used bandpass filter will be considered, where the remaining dominant second-order effects of the OA's GB products will be minimized by choosing appropriate element spreads satisfying the technology. This results in a bandpass filter which has better performance than any other actively compensated filters. The comparison of the results and experimental results follow to prove some of the conclusions made in this paper.