Sinewave Histogram Research Articles

Wavelet decomposition and reconstruction-based INL method for testing high-precision ADC

In traditional analog-to-digital converter (ADC) linearity testing, the cost of testing escalates in tandem with the increase in ADC resolution. This research proposes a time-efficient method for testing the integral nonlinearity (INL). Drawing on the wavelet decomposition and reconstruction technique in conjunction with sine wave histogram, our approach facilitates swift and accurate testing of high-precision ADC linearity compared to conventional methods. Our approach acquiring the initial INL result by sampling the sinusoidal histogram using a modest number of samples. Subsequently, we employ wavelet decomposition to break down the initial result into high-frequency and low-frequency portions. Setting thresholds for these components and reconstruct them to derive an accurate INL result. Experimental findings demonstrate that our proposed method effectively enhances the accuracy of high-precision ADC linearity testing. Furthermore, it reduces the linearity testing time by over tenfold and diminishes estimation errors by more than 30%. Consequently, our method establishes a more dependable means of testing for ADC design and manufacturing.

An Improved Sine Wave Histogram Test Method for ADC Characterization

This paper presents a modified version of the sine wave histogram test for analog-to-digital converter (ADC) characterization. To accurately estimate the transition levels, the input signal has to fulfill strict conditions, which are coherent sampling and uniform distribution of the phases. Noncoherent sampling of the sine wave leads to systematic errors in the transition level estimation, while the nonuniform distribution of the phases increases the variance of the results using the original sine wave histogram test method. The source of the errors is the improper modeling of the histogram of the measured signal. This paper shows that the true histogram of the measured sine wave can be reconstructed by estimating the phases of the sampled signal. It is shown that integrating this information into the estimation of the transition levels can significantly decrease the effect of noncoherent sampling, thus the ADC can be characterized accurately even if the conditions are not fulfilled. The proposed method is verified on both simulated and real measurement data.

An Output Response Analyzer Circuit for ADC Built-in Self-Test

In this paper, a structure of the output response analyzer (ORA) circuit for analog-to-digital converters (ADCs) built-in self-test (BIST) is presented. The ADC static parameters, i.e., offset error, gain error, and nonlinearity errors, are directly obtained from the sine-wave histogram test. Then, the obtained static parameters are related to estimate the degradation of signal-to-noise ratio (SNR) value. The appropriate approximations of the testing parameters reduce difficulties in designing the complete ORA circuit. In addition, the feature of reusable hardware in the calculation of sine-wave reference histograms and the computing capability of ADCs' parameters further improves the ORA design. This design is compact and easily to be adjusted by different setting. The developed ORA circuits are synthesized in a 0.18-μm technology to analyze the outputs of an 8-bit ADC to verify the designs.

A Histogram-Based Testing Method for Estimating A/D Converter Performance

A sine-wave histogram-testing structure for analog-to-digital converters (ADCs) is proposed. The ADC static parameters, i.e., offset error, gain error, and nonlinearity errors, are directly obtained from the sine-wave histogram test. Then, the obtained static parameters are related to the estimation of the degraded signal-to-noise ratio (SNR) value. Therefore, the relationships among these parameters are analyzed, and a single sine-wave histogram test can be performed to evaluate the ADC. With the appropriate approximations in the reference sine-wave histograms and the estimations of the ADC parameters, the realization of an ADC output analyzer circuit could be a simple task. An ADC output analyzer circuit is therefore developed and synthesized using a 0.18-mum technique to analyze the outputs of an 8-bit ADC and estimate its performances using the proposed method.

Histogram Tests for Wideband Applications

Characterization and testing of analog-to-digital converters (ADCs) are important for many reasons. A histogram test is a common method to characterize the linearity features of an ADC. Two commonly used stimulus signals are sine waves and Gaussian noise. This paper presents a metrological comparison between Gaussian and sine-wave histogram tests for wideband applications, that is, we evaluate the performance of the characterization of the ADC and the usability of postcorrection. A postcorrection procedure involves the characterization of the ADC nonlinearity and then the use of this information by processing the ADC output samples to remove the distortion. The results show that the Gaussian histogram test gives reasonable accuracy in measuring nonlinearities. However, it does not result in a suitable model for postcorrection in wideband applications. A single-tone sine-wave histogram will be a better basis for postcorrection. The best result can be obtained if the lookup table is trained with several single-tone sine waves in the frequency band.

Simple and Time-Effective Procedure for ADC INL Estimation

This paper deals with a novel testing technique aimed at estimating the accuracy of analog-to-digital converters (ADCs). The main advantage of the proposed approach is the higher testing speed, particularly the ability to achieve an accurate estimate of the low-frequency component (LCF) of the integral nonlinearity (INL) pattern of an ADC in a time that may be even one order of magnitude shorter than that of other standard techniques such as the sine wave histogram test (SHT). The estimation accuracy associated with the testing procedure is determined theoretically and validated by means of simulations and experimental results

Noise sensitivity of the exponential histogram ADC test

This paper deals with some error effects caused by additive noise at analogue-to-digital converters (ADCs) testing based on the histogram method and the exponential shape of input testing stimulus. The histogram method with the exponential stimulus has been an alternative test method for ADC that was developed by the authors of this paper. Here, the theoretical analysis of some errors in estimations of code bin widths and quantisation levels caused by additive input Gaussian noise is performed. The theoretical results are verified by simulations and experimental tests. Finally the noise sensitivity of the exponential histogram test method is compared with the known noise sensitivity of the standardised sinewave histogram test method.

Fast estimation of ADC nonlinearities using the Sinewave Histogram Test

The Sinewave Histogram Test (SHT) is a widely used standard technique to estimate the threshold voltages and the Integral NonLinearity (INL) pattern of Analog-to-Digital Converters (ADCs). The main drawback of the SHT is that, for a given target accuracy, the number of test samples as well as the testing time tend to increase exponentially as the resolution of the converter grows. The strategy described in this paper still relies on the SHT, but it enables a major reduction in testing time without affecting estimator accuracy provided that the INL pattern exhibits prevailingly a low code frequency content. This result can be achieved simply by suitably filtering the INL pattern obtained using a standard SHT over a reduced amount of test samples. After being justified theoretically, the proposed solution is validated by means of both simulations and experimental evidences.

Effective ADC linearity testing using sinewaves

This paper deals with the effectiveness of the sinewave histogram test (SHT) for testing analog-to-digital converters. The implementation is discussed, with respect to the adopted procedures and to the choice of relevant parameters. Some of the published approximations currently limiting the characterization of the test performance are removed. The statistical efficiency of the SHT is evaluated by comparing the associated estimator variance with the corresponding Crame/spl acute/r-Rao lower bound, theoretically derived assuming sinewaves corrupted by Gaussian noise. Finally, both simulation and experimental results are presented to validate the proposed approach.

Statistical efficiency of the ADC sinewave histogram test

This paper presents an analysis of the statistical efficiency of the sinewave histogram test used for estimating the unknown transition levels of an analog-to-digital converter. Accordingly, at first, a closed-form determination of the Cramer-Rao bound is derived under the assumption of a noiseless stimulus signal. Both unbiased and biased versions of the bound are described in order to account for the eventual bias introduced by commonly employed estimators. Then, additive Gaussian noise is assumed, and comments are made about its effects on the maximum achievable accuracy.

ADC sinewave histogram testing with quasi-coherent sampling

In this paper, the accuracy of ADC sinewave histogram testing is analyzed under the assumption of quasicoherent sampling. A bound is derived on the inaccuracy in setting the ratio between sinewave and sampling frequencies, which allows the design of the test for prescribed levels of estimator variance. Detailed proofs and simulation results are presented.

Design of ADC sinewave histogram test

In this paper, sinewave histogram test is considered as a method for the estimation of analog-to-digital converter (ADC) integral nonlinearities. The issues related to the design of test parameters are also discussed with respect to already published directions on this topic. Moreover, particular emphasis is dedicated to the problem of estimating standard uncertainty in accordance with international standards.

ADC compensation using a sinewave histogram method

The need for high dynamic range analog to digital converters (ADCs) is strong due to the growing use of digital signal processing in communications applications. ADC performance has improved over the years due to advances in both design concepts and semiconductor technologies. However most ADCs still still exhibit undesirable distortion in addition to quantization error, thus limiting spurious free dynamic range, (SFDR), in digital receiver applications. This paper describes a new method for developing ADC error function models using standard sinewave histogram methods. The method provides better error representation by providing error basis functions for every state. Results show this method is capable of removing all slope dependent errors in complex ADC error models and application to a 200 MSPS ADC showed more than 10 dB improvement in SFDR over the full Nyquist band for the ADC.

Using sine wave histograms to estimate analog-to-digital converter dynamic error functions

This paper describes a new method for developing analog-to-digital converter (ADC) error function models using modified sinewave histogram methods. The error models may be used to digitally compensate for nonlinearities introduced by the converter. The histogram modification involves sorting of converter output samples based upon an estimated associated input derivative signal. This error model is based upon a previously unpublished result which shows that sinewave histograms yield distinctly different expected errors for each state based upon input signal slope associated with each output sample. This result thus provides a dynamic dependence for expected errors measured by means of histogram methods. Sorted sinewave histograms are used to estimate slope dependent expected errors at each ADC output state (code). The method provides improved error representation by providing error basis functions for every output code. Simulated results prove that this method removes all slope dependent errors for complex ADC architectures while experimental results for an 8-bit 200 MSPS ADC yielded more than 10 dB improvement in spurious-free-dynamic-range (SFDR) over the full Nyquist band. The new method is thus shown to possess wideband dynamic error character.