SiN Capping Layer Research Articles

Improved gate reliability of normally off p-GaN gate HEMTs with in situ SiN cap-layer

Improved gate reliability of normally off p-GaN gate HEMTs with <i>in situ</i> SiN cap-layer

Enhanced device performance of GaN high electron mobility transistors with in situ crystalline SiN cap layer

In this paper, a ∼2 nm in situ SiN cap layer on AlGaN barrier layer is grown, which is revealed to be crystalline using high-resolution cross-sectional transmission electron microscopy. Benefitting from superior interface quality of epitaxial crystalline SiN/AlGaN interface, the gate diodes with in situ SiN cap layer feature lower interface trap state density than that with GaN cap layer. By comparing the GaN high electron mobility transistors (HEMTs) with the conventional GaN cap layer, the GaN HEMTs with in situ SiN cap layer exhibit improved device performance, showing higher electron mobility, higher drain current, larger on/off current ratio, and higher transconductance. For breakdown characteristics, the devices with in situ crystalline SiN cap layer show prominent advantages over the GaN cap layer with a 30% breakdown voltage increase to 810 V.

Plasma induced damage on AlGaN/GaN heterostructure during gate opening for power devices

During the fabrication of metal oxide semiconductor high electron mobility transistor based on AlGaN/GaN heterostructure, gate patterning is recognized as the most critical step that can lead to electrical degradation of the transistor. In this work, we performed the SiN cap layer plasma etching processes by two fluorine-based plasma processes (SF6/Ar and CHF3/CF4/Ar) with low (≈15 eV) and high (≈260 eV) ion energies. Moreover, we investigate the postetching treatment using a KOH solution in order to restore the quality of the AlGaN barrier surface after etching. The objective of this article is to evaluate the AlGaN barrier surface damage after the listed plasma etching processes and postetching strategies by using quasi-in situ angle-resolved x-ray photoelectron spectroscopy, transmission electron microscopy, and atomic force microscope. Accordingly, it is found that both high ion energy plasma processes lead to a significant stoichiometric change and modification of the AlGaN barrier layer into a 1.5 nm F-rich AlGaNFx subsurface reactive layer. The decrease in ionic energy leads to a decrease in the SiN etch rate and a significant improvement in the SiN/AlGaN etch selectivity (which becomes infinite) for both plasma chemistries. Moreover, the decrease in ion energy decreases the depth of the modification (about 0.5 nm) and reduces the stochiometric change of the AlGaN barrier layer. However, both low and high ion energy SF6/Ar plasma lead to 0.8 eV Fermi level shift toward the valence band. Furthermore, the KOH postetching treatment demonstrates complete and effective removal of the AlGaNFx subsurface reactive layer and restoration of the surface properties of the AlGaN layer. However, this removal leads to AlGaN recesses that are correlated to the thickness of the reactive layer formed during the etching.

Improved Breakdown Voltage and Low Damage E-Mode Operation of AlON/AlN/GaN HEMTs Using Plasma Oxidation Treatment

Low-damage plasma oxidation treatment for AlN/GaN high-electron-mobility transistors (HEMTs) was developed in this letter, with which high-performance enhancement-mode (E-mode) AlON/AlN/GaN HEMTs were demonstrated. After removal of in situ SiN cap layer within gate area, remote plasma oxidation (RPO) treatment of 4.9nm AlN barrier layer at 300 °C leads to formation of AlON insulator layer and effective depletion of 2-D electron gas channel, without etch-induced damage or serious interfacial issues compared with the commonly used gate- recess metal-insulator-semiconductor HEMTs. Thanks to the low-damage RPO treatment, the achieved E-mode HEMTs with threshold voltage of 0.4 V exhibit quite a small loss of output current (7.8%) compared with the depletion-mode devices. In addition, the AlON gate insulator layer results in a remarkable increase in breakdown voltage of devices from 20 V to 74 V, which benefits the high-voltage operation of AlN/GaN technology. Further investigation shows that the oxidation process of AlN barrier tends to be saturated with treatment time increasing, providing a promising solution to the high-performance E-mode operation of scaled GaN-based HEMTs in RF applications.

Comparative Study of the New Type Capping Layer for Hf0.5Zr0.5O2 Ferroelectric Film

The capping layers have great influences on the ferroelectricity of the Hf0.5Zr05O2 (HZO) film during annealing process. In this paper we compared the properties of the HZO film with two inorganic nonmetallic capping layers and no capping layer. The remnant (2Pr) of HZO films are 23.5 uC/cm2, 27.3 uC/cm2 and 20.3 uC/cm2 for no capping layer, Si3N4 capping layer and SiO2 capping layer, respectively. The capping layer can change the direction of the coercive filed shift even though the capacitors have the same metal electrodes.

Influences of etching chemical parameters on AlGaN/GaN electrical degradation in power devices

The influence of chemical parameters on electrical degradation in an AlGaN/GaN heterostructure was investigated in order to improve performance in metal-oxide-semiconductor high-electron mobility transistor devices. We first examined the influence of plasma chemistry on electrical degradation by using different plasma chemistries for the SiN capping layer opening and comparing the results. The full standard chemistry was evaluated in order to determine the impact of each gas on the degradation. Rsheet and x-ray photoelectron microscopy characterizations and simulations were performed to better understand how light elements such as helium penetrate deeply into the heterostructure and degrade its electrical characteristics. The materials used as masks were also studied. A photoresist mask and a SiN mask were compared on an AlGaN/GaN heterostructure during plasma processing. Electrical degradation was always greater in the presence of a resist due to the decomposition of the resist under the plasma causing hydrogen to be released into the plasma. Simulation of hydrogen implantation in AlGaN was also performed to understand its impact on electrical performance.

Characterization of AlGaN/GaN degradations during plasma etching for power devices

During the fabrication of a MOS-HEMT, the plasma-etching steps are critical because they can damage the GaN materials and lead to electrical degradation effects. To address these limitations, we studied the influence of plasma parameters on electrical degradation in an AlGaN/GaN heterostructure. In this work, the modifications induced by bias-voltage applied during the SiN capping layer opening are investigated. Physical (XRD, XRR, AFM and TEM) and chemical (XPS) characterizations have been performed to have a better understanding this plasma parameter on GaN damage. These results are correlated with Rsheet measurements to evaluate the electrical degradation in the heterostructure. Finally, degradation mechanisms and recommendation have been proposed to improve the plasma etching process.

Impact of Gate–Drain Spacing on Low-Frequency Noise Performance of &lt;italic&gt;In Situ&lt;/italic&gt; SiN Passivated InAlGaN/GaN MIS-HEMTs

In this paper we investigated the gate–drain access region spacing ( $L_{\mathrm {GD}})$ effect on electrical and noise performance of InAlGaN/GaN metal–insulator–semiconductor high electron mobility transistors (MIS-HEMTs) using in situ SiN cap layer as gate insulator. Different $L_{\mathrm {GD}}$ of InAlGaN/GaN MIS-HEMTs using sub-10 nm barrier layer are studied. Low-frequency noise measurements have been carried out for the first time in order to analyze the impact of the gate–drain spacing on the electrical characteristics. The noise of the channel under the gate has been identified as the dominant channel noise source for $L_{\mathrm {GD}} . Finally, the calculated Hooge parameter ( $\alpha _{H})$ is equal to $3.1\times 10^{-4}$ . It reflects the high material quality while using sub-10 nm InAlGaN layer, which is promising for high-frequency applications.

High power, high PAE Q-band sub-10 nm barrier thickness AlN/GaN HEMTs

We report a state-of-the-art performance of deep sub-micrometer gate length AlN/GaN High Electron Mobility Transistors using a thick in situ SiN cap layer. With 120 nm gate length large-signal load-pull measurements showed a peak power-added-efficiency (PAE) above 45%. To the best of our knowledge, this represents the highest PAE for GaN HEMTs at 40 GHz, especially when using a sub-10 nm barrier thickness. Furthermore, state-of-the-art peak output power density above 6 W mm−1 at 40 GHz has been achieved in pulsed mode. This is the highest output power ever reported for sub-10 nm barrier thickness Q-Band GaN devices. The performance improvement is attributed to the thick in situ SiN cap layer and optimized electron confinement allowing higher voltage operation and lower dispersion under high electric field.

Correlating thermoelectric properties with microstructure in Bi0.8Sb0.2 thin films

The room temperature electronic transport properties of 100 nm-thick thermoelectric Bi0.8Sb0.2 films, sputter-deposited onto quartz substrates and post-annealed in an ex-situ furnace, systematically correlate with the overall microstructural quality, improving with increasing annealing temperature until close to the melting point for the alloy composition. The optimized films have high crystalline quality with ∼99% of the grains oriented with the trigonal axis perpendicular to the substrate surface. Film resistivities and Seebeck coefficients are accurately measured by preventing deleterious surface oxide formation via a SiN capping layer and using Nd-doped Al for contacts. The resulting values are similar to single crystals and significantly better than previous reports from films and polycrystalline bulk alloys.

Combined plasma-enhanced-atomic-layer-deposition gate dielectric and in situ SiN cap layer for reduced threshold voltage shift and dynamic ON-resistance dispersion of AlGaN/GaN high electron mobility transistors on 200 mm Si substrates

In this work we will present the experimental path followed to optimize the dynamic ON-resistance (RDS-ON) dispersion and to reduce the threshold voltage shift of AlGaN/GaN transistors grown on 200 mm Si wafers. Firstly, it will be demonstrated that a SiN gate dielectric grown by means of plasma enhanced atomic layer deposition (PEALD) instead of rapid thermal chemical vapor deposition (RTCVD) reduces threshold voltage (Vth) shift induced by negative gate bias and the gate leakage. Secondly, the dynamic RDS-ON dispersion of two wafers with same gate dielectric (PEALD SiN) but different in situ metal organic chemical vapor deposition (MOCVD) capping layer, GaN or SiN, is compared. Results will show that the traps at the surface causing the RDS-ON dispersion can drastically be reduced by using in situ MOCVD SiN.

High resolution secondary ion mass spectrometry analysis of hydrogen behavior in SiO2/SiN/SiO2 films with thermal treatment

The distribution and behavior of hydrogen in a SiO2/SiN/SiO2 (ONO) film stack structure with thermal treatment were investigated by high-resolution secondary ion mass spectrometry analysis. Hydrogen atoms were present in the poly-Si/top-SiO2 interface, SiN layer, and bottom-SiO2/Si-substrate interface. These hydrogen atoms decreased in number with annealing (1000 °C, 60 s) and spike annealing (1000 °C, about 1 s). However, when a SiN cap layer with hydrogen atoms was formed on a poly-Si/ONO film structure, hydrogen atoms in the ONO film did not decrease in number with spike annealing. It was considered that the SiN cap layer mainly performed a supply source of hydrogen into the ONO film during spike annealing, and that hydrogen atoms interdiffused between the SiN cap layer and the SiN layer of the ONO film. These results indicate that the amount of hydrogen in the ONO film can be controlled by annealing and the formation of a SiN cap layer.

Characterization of surface defects on Be-implanted GaSb

Characteristics of ion implantation induced damage in GaSb, and its removal by rapid thermal annealing, are investigated by cross-sectional transmission electron microscopy. Rapid thermal annealing (RTA) has been implemented on implanted GaSb for various temperatures and durations with the semiconductor capped, which avoids Sb out-diffusion and Ga agglomeration during the process. The RTA damage induced in the GaSb wafer was studied by scanning electron microscopy and energy dispersive x-ray spectroscopy. The results of the microscopy study were then used to optimize the RTA recipe and the Si3N4 capping layer thickness to achieve doping activation while minimizing crystalline damage. Results indicate a lattice quality that is close to pristine GaSb for samples annealed at 600 °C for 10 s using 260 nm thick Si3N4 capping layer. Secondary ion mass spectrometry measurement indicates that the implanted Be does not migrate in the GaSb at the used annealing temperature. Finally, electrical characteristics of diodes fabricated from the implanted material are presented that exhibit low series resistance and high shunt resistance suitable for photovoltaic applications.

Ultrathin (8-14 nm) Conformal SiN for sub-20 nm Copper/Low-k Interconnects

A multilayer SiN barrier film with high breakdown field and low leakage current is developed for Cu low-k interconnects and is compared with the SiCNH barrier film used in previous technology nodes. Ultrathin SiN barrier cap films also provide high conformality and fill recessions in Cu lines as observed after CMP. The conformal ultrathin (8-14 nm) multilayer SiN cap is robust with higher breakdown field, lower leakage and forms a good oxidation barrier. The electromigration activation energy for a SiN cap layer of 10-12 nm dielectric thickness is about 0.9 eV.

Reduction of threading dislocation by recoating GaN island surface with SiN for high‐efficiency GaN‐on‐Si‐based LED

AbstractWe have demonstrated low‐threading‐dislocation‐density (low‐TDD) GaN grown on Si substrate using the technique of multiple modulation of dislocation behavior that combines GaN island formation on SiN interlayer with recoating GaN island surface with SiN cap layer. TEM analysis showed the dislocation bending and/or blocking is brought about at the surface of GaN islands by recoating GaN island surface with SiN cap layer. TDD was found to be as low as 2.6×108/cm2 with FWHMs of 289 and 256 arcsec for (0002) and (10–12) X‐ray rocking curves (XRCs), respectively, which is a value comparable to that for GaN grown on a sapphire substrate. By reducing TDD, the light output power at 20 mA (12.5 A/cm2) was enhanced by a factor of 1.5 and the maximum EQE increased up to 59% for the blue LED. This result indicates that the reduction of TDD is an effective approach for obtaining the high‐efficiency GaN‐on‐Si‐based LED. (© 2014 WILEY‐VCH Verlag GmbH &amp; Co. KGaA, Weinheim)

Evaluation for interface strength fluctuations induced by inhomogeneous grain structure of Cu line in LSI Interconnects

Local adhesion strength of the interface between Cu line and SiN cap layer in a Cu damascene interconnect structure of LSI has a significant fluctuation when evaluated with in-plane dimensions of 1×1 μm specimens, which was 4.78±1.63 J/m2. The reproducibility of the evaluation technique was investigated by evaluating the strength of the Cu/SiN interface for the specimens fabricated on a plate of Cu single crystal, where the interface strength was measured as 0.62±0.02J/m2. The relative standard deviation of interface strength distribution in LSI interconnect structure was 34% which was more than ten times larger than the value 2.5% for the specimens fabricated on the plate of Cu single crystal. The significant fluctuation of interface strength was induced clearly not by the random error of the evaluation technique, but by the inhomogeneous grain structure of Cu line with various crystal orientations and grain boundaries. By means of elastic-plastic interface crack extension simulations, it was revealed that the difference in the amount of energy dissipated in plastic deformation of Cu layer mainly leads to a significant fluctuation of the apparent strength. Plastic deformation of Cu layer plays a dominant role on the local strength of interface Cu/SiN in LSI interconnects.

Pattern transfer of directed self-assembly patterns for CMOS device applications

A study on the optimization of etch transfer processes using 200-mm-scale production type plasma etch tools for circuit relevant patterning in the sub-30-nm pitch regime using directed self-assembly (DSA) line–space patterning is presented. This work focuses on etch stack selection and process tuning, such as plasma power, chuck temperature, and end point strategy, to improve critical dimension control, pattern fidelity, and process window. Results from DSA patterning of gate structures featuring a high-k dielectric, a metal nitride and poly Si gate electrode, and a SiN capping layer are also presented. These results further establish the viability of DSA pattern generation as a potential method for Complementary metal–oxide–semiconductor (CMOS) integrated circuit patterning beyond the 10-nm node.

Experimental and numerical evaluation of interfacial adhesion on Cu/SiN in LSI interconnect structures

The local interfacial strength is a key factor in designing and fabricating advanced three-dimensional large-scale integration interconnect structures. In this paper, both local fracture tests and three-dimensional elastic–plastic crack propagation analysis for a 10μm×10μm specimen were performed, and the local interfacial adhesion between a Cu interconnect and a SiN cap layer were evaluated. The three-dimensional elastic–plastic crack propagation simulation was developed to evaluate the interfacial adhesion that eliminated the effect of progressive plastic dissipation energy during crack propagation. The results show that the average interfacial adhesion for Cu/SiN is 4.46±0.17J/m2. The crack propagation behavior and fracture pattern depend on the interfacial adhesion, and these differences are due to the plastic yielding of the side edge of the specimen. The critical interfacial adhesion for the onset of shear fracture is 4.92J/m2, which is the upper bound of the interfacial adhesion evaluation for the 10μm×10μm specimen.

Hydrogen Instability Induced by Postannealing on Poly-Si TFTs

This brief investigates hydrogen instability induced by postannealing. Results show that using a SiN capping layer can prevent the release of hydrogen from a polycrystalline-silicon channel. However, removing this SiN capping layer allows the hydrogen release during postannealing, and the resulting device performance becomes comparable to that of the control sample. Hydrogen release reduces the immunity of PBTI and NBTI. Two possible mechanisms can explain the increased preexisting defects associated with hydrogen release, which affects the NBTI and PBTI.

OS2406 半導体デバイス配線構造における局所付着強度分布の統計的評価の試み(OS24-2 三次元積層半導体チップにおけるシリコン貫通ビア/微細金属接合技術と強度信頼性,OS-24 三次元積層半導体チップにおけるシリコン貫通ビア/微細金属接合技術と強度信頼性)

A technique to evaluate local interface strength measured a considerable range of scatter in toughness of interface between Cu and SiN cap layer in LSI interconnect. In order to estimate the range of uncertainty in the evaluation procedure, the same technique was applied to the interface of vapor-deposited Au and native SiO_2 on a silicon wafer, which was expected to have a relatively homogeneous adhesion strength. By combining the obtained results with the statistical analysis, uncertainties in the evaluation procedure were evaluated and excluded from the scatter in the measurement results of Cu/SiN interface. Finally, the intrinsic fluctuation of interface strength due to the material properties was successfully determined.