HSPICE Research Articles

Regression Model-Based AMS Circuit Optimization Technique Utilizing Parameterized Operating Condition

An analog and mixed-signal (AMS) circuit that draws on machine learning while using a regression model differs in terms of the design compared to more sophisticated circuit designs. Technology structures that are more advanced than conventional CMOS processes, specifically the fin field-effect transistor (FinFET) and silicon-on-insulator (SOI), have been proposed to provide the higher computation performance required to meet various design specifications. As a result, the latest research on AMS design optimization has enabled enormous resource savings in AMS design procedures but remains limited with regard to reflecting the intended operating conditions in the design parameters. Hereby, we propose what is termed a supervised learning artificial neural network (ANN) as a means by which to define an AMS regression model. This approach allows for rapid searches of complex design dimensions, including variations in performance metrics caused by process–voltage–temperature (PVT) changes. The method also reduces the considerable computation expense compared to that of simulation-program-with-integrated-circuit-emphasis (SPICE) simulations. Hence, the proposed AMS circuit design flow generates highly promising output to meet target requirements while showing an excellent ability to match the design target performance. To verify the potential and promise of our design flow, a successive approximation register analog-to-digital converter (SAR ADC) is designed with a 14 nm process design kit. In order to show the maximum single ADC performance (6-bit∼8-bit resolution and few GS/s conversion speed), we have set three different ADC performance targets. Under all SS/TT/FF corners, ±6.25% supply voltage variation, and temperature variation from −40 ∘C to 80 ∘C, the designed SAR ADC using our proposed AMS circuit optimization flow yields remarkable figure-of-merit energy efficiency (approximately 15 fJ/conversion step).

Research on Device Modeling Technique Based on MLP Neural Network for Model Parameter Extraction

The parameter extraction of device models is critically important for circuit simulation. The device models in the existing parameter extraction software are physics-based analytical models, or embedded Simulation program with integrated circuit emphasis (SPICE) functions. The programming implementation of physics-based analytical models is tedious and error prone, while it is time consuming to run the device model evaluation for the device model parameter extraction software by calling the SPICE. We propose a novel modeling technique based on a neural network (NN) for the optimal extraction of device model parameters in this paper, and further integrate the NN model into device model parameter extraction software. The technique does not require developers to understand the device model, which enables faster and less error-prone parameter extraction software developing. Furthermore, the NN model improves the extraction speed compared with the embedded SPICE, which expedites the process of parameter extraction. The technique has been verified on the BSIM-SOI model with a multilayer perceptron (MLP) neural network. The training error of the NN model is 4.14%, and the testing error is 5.38%. Experimental results show that the trained NN model obtains an extraction error of less than 6%, and its extraction speed is thousands of times faster than SPICE in device model parameter extraction.

A Methodology to Assist in Improvements of Low-cost Electrical Impedance Tomography Systems

Electrical Impedance Tomography (EIT) is a technique that enables the reconstruction of the impedance distributions inside a vessel in a multiphase flow of industrial processes. Such a technique combines a data acquisition (DAQ) system to inject a current and to measure the voltages on the sensors and an inverse problem technique to reconstruct the image properly. This problem is highly ill-conditioned, causing errors to produce instabilities. Therefore, when performing the acquisition, the DAQ system must have adequate accuracy to allow the reconstruction of images with good quality. To avoid these measurement inaccuracies, this paper introduces a methodology that aid in the process of development of low-cost systems. It consists of investigating the errors in the current version of the system. Further, predicting the systematic errors of each subsystem by modeling its frequency response by Simulation Program with Integrated Circuit Emphasis (SPICE). From this information, it is possible to perform critical analysis, aiding design decisions.

Intelligent Detection Methods of Electrical Connection Faults in RF Circuits

Printed circuit boards (PCBs) have a large number of electrical connection nodes. Exposure to harsh environments may lead to connection faults in these nodes. In the present work, intelligent detection methods for electrical connection faults were studied. Specifically, the fault characteristics of connectors, bonding wires and solder balls in the frequency domain were analyzed. The reflection and transmission parameters of an example filter circuit with electrical connection faults were calculated using the Simulation Program with Integrated Circuit Emphasis (SPICE). With these obtained electrical parameters, three machine learning algorithms were used to detect example electrical connection faults for the example circuit. Based upon the performance evaluations of the three algorithms, one can conclude that machine-learning-based intelligent fault detection is a promising technique in diagnosing circuit faults due to electrical connection issues with high accuracy and lower time cost as compared to current manual processes.

Bandwidth extension method based on the field-shunting effect in a high-gain photoelectric receiver circuit.

In the high-gain photoelectric receiver circuit, the method based on the field-shunting effect is applied to improve the bandwidth of the transimpedance amplifier. This method is implemented by adding a ground trace under the gain resistor, which reduces the parasitic capacitance of the gain resistor and thus increases the bandwidth. To obtain the specific impact of this method on bandwidth, a series of simulations are carried out, including electromagnetic simulations of a three-dimensional structure of circuit gain part and simulation program with integrated circuit emphasis (SPICE) simulations of the high-gain voltage-current feedback transimpedance amplifier. Finally, the optimal simulation result shows that selecting a 1206 size chip fixed resistor and setting the ground trace width to 1.1 mm can greatly reduce the influence of resistor parasitic effects on the circuit, thereby achieving the best performance of bandwidth extension. Further, the comparative experiment also verifies the effectiveness of the method for bandwidth enhancement.

Simulations of hybrid charge-sensing single-electron-transistors and CMOS circuits

Single-electron transistors (SETs) have been extensively used as charge sensors in many areas, such as quantum computations. In general, the signals of SETs are smaller than those of complementary metal–oxide–semiconductor (CMOS) devices, and many amplifying circuits are required to enlarge the SET signals. Instead of amplifying a single small output, we theoretically consider the amplification of pairs of SETs, such that one of the SETs is used as a reference. We simulate the two-stage amplification process of SETs and CMOS devices using a conventional SPICE (Simulation Program with Integrated Circuit Emphasis) circuit simulator. Implementing the pairs of SETs into CMOS circuits makes the integration of SETs more feasible because of direct signal transfer from the SET to the CMOS circuits.

Fabrication, Characterization, and Modeling of an Aluminum Oxide-Gate Ion-Sensitive Field-Effect Transistor-Based pH Sensor.

The ion-sensitive field-effect transistor (ISFET) is a popular technology utilized for pH sensing applications. In this work, we have presented the fabrication, characterization, and electrochemical modeling of an aluminum oxide (Al2O3)-gate ISFET-based pH sensor. The sensor is fabricated using well-established metal–oxide–semiconductor (MOS) unit processes with five steps of photolithography, and the sensing film is patterned using the lift-off process. The Al2O3 sensing film is deposited over the gate area using pulsed-DC magnetron-assisted reactive sputtering technique in order to improve the sensor performance. The material characterization of sensing film has been done using x-ray diffraction, field-emission scanning electron microscopy, energy-dispersive spectroscopy, and x-ray photoelectron spectroscopy techniques. The sensor has been packaged using thick-film technology and encapsulated by a dam-and-fill approach. The packaged device has been tested in various pH buffer solutions, and a sensitivity of nearly 42.1 mV/pH has been achieved. A simulation program with integrated circuit emphasis (SPICE) macromodel of the Al2O3-gate ISFET is empirically derived from the experimental results, and the extracted electrochemical parameters have been reported. The drift and hysteresis characteristics of the Al2O3-gate ISFET were also studied, and the obtained drift rates for different pH buffer solutions of 4, 7, and 10 are 0.136 μA/min, 0.124 μA/min, and 0.108 μA/min, respectively. A hysteresis of nearly 5.806 μA has been obtained. The developed sensor has high sensitivity along with low drift and hysteresis.

An artificial neural network chip based on two-dimensional semiconductor

Recently, research on two-dimensional (2D) semiconductors has begun to translate from the fundamental investigation into rudimentary functional circuits. In this work, we unveil the first functional MoS2 artificial neural network (ANN) chip, including multiply-and-accumulate (MAC), memory and activation function circuits. Such MoS2 ANN chip is realized through fabricating 818 field-effect transistors (FETs) on a wafer-scale and high-homogeneity MoS2 film, with a gate-last process to realize top gate structured FETs. A 62-level simulation program with integrated circuit emphasis (SPICE) model is utilized to design and optimize our analog ANN circuits. To demonstrate a practical application, a tactile digit sensing recognition was demonstrated based on our ANN circuits. After training, the digit recognition rate exceeds 97%. Our work not only demonstrates the protentional of 2D semiconductors in wafer-scale integrated circuits, but also paves the way for its future application in AI computation.

Modulation Performance Enhancement of Directly Modulated Injection-Locked Semiconductor Lasers Using an Equivalent Electrical Circuit

We propose an equivalent electrical circuit model to evaluate the direct modulation performance of optically injection-locked (OIL) semiconductor lasers. We modeled the equivalent circuit of the OIL laser based on alternating complex envelope representations, simulated it using the Simulation Program with Integrated Circuit Emphasis (SPICE), and analyzed the frequency response of the OIL laser. Although the frequency response of the OIL laser is better than that of a free-running laser, its 3-dB modulation performance is degraded by the relaxation oscillation that occurs during direct modulation of the semiconductor laser. To overcome this limitation and maintain the maximum modulation performance within the entire locking range, we also designed an electrical filter to preprocess the electrical modulation signal and compensate for the non-flat modulation output of the OIL laser. The damping ratio of the directly modulated OIL laser increased by 0.101 (280%) and its settling time decreased by >0.037 (44%) when the electrical compensation circuit was added, exhibiting a flat 3-dB modulation bandwidth of 28.79 GHz.

Statistical Learning of IC Models for System-Level ESD Simulation

To enable accurate system-level electrostatic discharge (ESD) simulation, this article applies statistical learning to obtain I/O port models of the victim integrated circuits (ICs). A quasi-static <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">I–V</i> model derived using kernel regression can capture the circuit board dependency of the behavior observed at the I/O pin, regardless if there is snapback. The non-parametric kernel model can be reduced to a system-specific parametric model, which has smaller requirements for computing time and memory. In some cases, transient system-level ESD simulation may require the IC model to replicate the dynamic behavior of the nonlinear circuit. A recurrent neural network is demonstrated to be a suitable model in such cases. This article provides a detailed RNN training flow for IC pin modeling, and presents a Verilog-A implementation of the RNN for use with Simulation Program with Integrated Circuit Emphasis (SPICE)-type simulators.

A High-Speed Bipolar Hybrid Cockcroft–Walton/Dickson Multiplier for Shockwave Non-thermal Food Processing

For the design of shockwave non-thermal food processing systems, a novel high-speed bipolar voltage multiplier is presented in this paper. Unlike conventional high voltage multipliers, the proposed voltage multiplier has bipolar topology employing hybrid Cockcroft-Walton/Dickson multipliers (HCWDMs), where the bipolar HCWDM is driven by a driver circuit generating high speed rectangular pulses. Therefore, the proposed multiplier can achieve high speed operation. Through simulation program with integrated circuit emphasis (SPICE) simulations and experiments, the validity of the proposed multiplier is confirmed. The SPICE simulations and experiments reveal that the proposed multiplier outperforms the conventional HCWDM.

Predicting Early EVA Degradation in Photovoltaic Modules From Short Circuit Current Measurements

One of the common failures in photovoltaic modules is the degradation of the ethylene-vinyl acetate (EVA) encapsulant due to prolonged ultraviolet exposure and other environmental stress factors, such as temperature and humidity. Experimental studies have shown that significant reduction in the optical transmission due to EVA degradation leads to loss in the available power by more than 50%. In this article, a novel approach to predict the early degradation of EVA encapsulant is proposed by correlating EVA degradation with short-circuit current (I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">SC</sub> ). An electrical circuit simulator, simulation program with integrated circuit emphasis (SPICE), is used to evaluate the short-circuit current obtained under varying optical transmission caused by EVA discoloration. The simulation follows three steps: simulation of the transmitted solar spectrum; simulation of the spectral short-circuit current density; and simulation of the current-voltage (I-V) curve to obtain short-circuit current (I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">SC</sub> ), maximum power output (P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">max</sub> ), open-circuit voltage (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OC</sub> ) and fill factor. Results show that the reduction in short-circuit current due to EVA degradation differs from the reductions expected due to a spectrally-uniform reduction of intensity of the solar irradiance. Both types of variation are linear, however, the slope due to EVA degradation is larger than the slope obtained for normal intensity variations in the solar irradiance. This model, when applied in conjunction with solar irradiance measurements, can predict early onset of EVA encapsulant failure, thereby enabling preventative measures to be taken.

Modeling of Bias-Dependent Effective Velocity and Its Impact on Saturation Transconductance in AlGaN/GaN HEMTs

In this article, we present a surface-potential-based approach to model the bias-dependent effective velocity observed in AlGaN/GaN high-electron-mobility transistors (HEMTs) due to optical phonon scattering. Our model precisely reproduces the progressive decrease in the saturation velocity in GaN HEMTs with increasing gate voltages, as reported in the literature, which is predominantly due to the scattering of electrons, forming the high-density two-dimensional electron gas (2DEG), by optical phonons at high overdrive voltages. We show that this dependence differs from the traditional mobility degradation models in terms of its impact on the device current-voltage (I- V) characteristics and illustrate how the inclusion of a velocity saturation model also provides the model users with an additional handle for parameter extraction. The model is explicit and, by virtue of its Simulation Program with Integrated Circuit Emphasis (SPICE) compatibility, is readily implemented in the industry-standard Advanced SPICE Model for HEMTs (ASM-HEMTs) model and has been validated against experimental dc I-V and RF S-parameter measurements of an in-house GaN device.

Custom measurement system for memristor characterisation

A cheap, compact and customisable characterisation system for memristor devices, working between ± 10 V, is presented. SPICE (Simulation Program with Integrated Circuit Emphasis) simulations are performed to verify the circuit feasibility and a proper software is developed to drive the system. The potentiality of the realised system is tested by performing several electrical measurements on both Cu/HfO2/Pt memristors and two-terminals commercial devices.

Investigation of negative DIBL effect for ferroelectric-based FETs to improve MOSFETs and CMOS circuits

In this study, negative DIBL (NDIBL) due to negative capacitance is used to improve MOSFETs and Complementary Metal-Oxide-Semiconductor Transistor (CMOS) circuits by employing custom-built Simulation Program with Integrated Circuit Emphasis (SPICE) model. A multi-threshold technique was proposed by using NDIBL effect, and it can be manufactured by simple manufacturing process without increasing footprint of transistor. The influence of the negative DIBL effect of a negative capacitance field-effect-transistor (NCFET) on transistor effective drive current (Ieff) and CMOS circuit performance were analyzed. The results shown that increasing NDIBL effect increased Ieff by ~12%. A 7-stage ring oscillator (RO) was simulated to analyze the CMOS circuit energy-delay, and it shown that significant delay reduction, at iso-energy and iso-area, can be achieved owing to NDIBL effect of NCFET. A 6T Static Random-Access Memory (SRAM) cell was investigated, and enhanced hold and read static noise margins (SNM) are achieved owing to NDIBL effect. Moreover, several methods of increasing NDIBL effect were proposed.

Transient analysis of graphene-based on-chip interconnects using closed-form MRA model

As interconnects in very-large-scale-integration technology shrinks into the sub-22 nm regime, carbon nanotubes, graphene nanoribbons (GNRs), and Cu-GNRs are emerging as potential replacements for conventional copper on-chip interconnects. This paper presents an matrix-rational-approximation (MRA) model for the fast transient analysis of graphene-based on-chip interconnects. The proposed model’s key feature is that it allows the mathematical representation of the transfer function matrix of on-chip graphene-based interconnect networks in the frequency-domain using closed-form rational functions. The network’s rational functions coefficients are derived from per-unit-length parameters and predetermined coefficients of the Padé approximation. The graphene-based network’s time-domain model is directly obtained from the rational function frequency-domain model without any numerical integration techniques. This makes the proposed MRA model more numerically efficient than conventional simulation program with integrated circuit emphasis (SPICE) models. The results obtained using the proposed model show less than 1% error when compared with HSPICE simulations, ensuring the proposed model’s excellent accuracy. A wide eye-height of 0.8137 V and eye-width of 219.87 ps are obtained for the eye-diagram analysis of multilayer graphene nanoribbon lines at 4 Gbps.

Accurate Circuit-Level Modelling of IGBTs with Thermal Phenomena Taken into Account

This paper proposes a new compact electrothermal model of the Insulated Gate Bipolar Transistors (IGBT) dedicated for SPICE (Simulation Program with Integrated Circuit Emphasis). This model makes it possible to compute the non-isothermal DC characteristics of the considered transistor and the waveforms of terminal voltages and currents of the investigated device and its internal temperature at transients. This model takes into account the nonlinearity of thermal phenomena in this device. The form of the formulated model is described and the problem of estimating its parameter values is discussed. The correctness of the proposed model was verified experimentally both at DC operation and at transients. The obtained results are compared to the results of computations performed with the use of the classical literature model. A very good agreement between the results of measurements and computations performed with the new model is obtained at different cooling conditions and in a wide range of changes of parameters characterising the electrical excitation of the tested device.

Influence of the Semiconductor Devices Cooling Conditions on Characteristics of Selected DC–DC Converters

The problem of an influence of cooling conditions of power semiconductor devices on properties of selected DC–DC converters is considered. The new version of electrothermal average model of a diode-transistor switch for SPICE (Simulation Program with Integrated Circuit Emphasis) is used in the investigations. This model makes it possible to take into account thermal inertia of semiconductor devices as well as mutual thermal interactions between these devices. The investigations are performed for boost and buck converters containing the power MOS (Metal-Oxide-Semiconductor) transistor and the diode. Computational results obtained using the proposed model are shown and discussed. Particularly, an influence of thermal phenomena in the diode and the power MOS transistor on the converters output voltage and internal temperature of the semiconductor devices is considered. The correctness of the selected results of computations was verified experimentally.

Towards Monolithic Indium Phosphide (InP)-Based Electronic Photonic Technologies for beyond 5G Communication Systems

This review paper reports the prerequisites of a monolithic integrated terahertz (THz) technology capable of meeting the network capacity requirements of beyond-5G wireless communications system (WCS). Keeping in mind that the terahertz signal generation for the beyond-5G networks relies on the technology power loss management, we propose a single computationally efficient software design tool featuring cutting-edge optical devices and high speed III–V electronics for the design of optoelectronic integrated circuits (OEICs) monolithically integrated on a single Indium-Phosphide (InP) die. Through the implementation of accurate and SPICE (Simulation Program with Integrated Circuit Emphasis)-compatible compact models of uni-traveling carrier photodiodes (UTC-PDs) and InP double heterojunction bipolar transistors (DHBTs), we demonstrated that the next generation of THz technologies for beyond-5G networks requires (i) a multi-physical understanding of their operation described through electrical, photonic and thermal equations, (ii) dedicated test structures for characterization in the frequency range higher than 110 GHz, (iii) a dedicated parameter extraction procedure, along with (iv) a circuit reliability assessment methodology. Developed on the research and development activities achieved in the past two decades, we detailed each part of the multiphysics design optimization approach while ensuring technology power loss management through a holistic procedure compatible with existing software tools and design flow for the timely and cost-effective achievement of THz OEICs.

Quasi-Static Partial Inductance for Open and Closed Loops

In the conventional partial element equivalent circuit (PEEC) method, all partial inductances are connected at both ends to other circuit elements of a PEEC or modified nodal approach (MNA), simulation program with integrated circuit emphasis (SPICE) type circuit. This article shows that if at least one end of a partial inductance remains without a connected element, it is called an open loop, which is also physical and is theoretically closed by displacement current. It is shown in this article that the open loop is only consistent if the partial inductance is evaluated using the Coulomb gauge; else, the magnetic energy computation of open loop is inconsistent. This article focuses on the difference and presents an analytical method for the calculation of partial inductance with Coulomb gauge in quasi-static field to figure it out. This difference is proven to be related to the calculation of vector potential <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">A</i> , whereas existing calculation is based on Lorentz gauge. Then, analytical results of conductor segments are derived for comparison of the two different gauges, and show the difference. Also, numerical experiments of the self- and mutual-partial inductances of conductor segments in open-loop problems are given for further comparison. The results illustrate that the proposed method is consistent with magnetic energy, and could be directly be applied to closed-loop problems without affecting the validity of the PEEC method. This method is believed to be an effective supplement in physical sense of partial inductance.