Simulation Of Phase-locked Loops Research Articles

Benchmarking simulation and theory of various PLLs produce orthogonal signals under abnormal electric grid conditions

The voltage or current harmonics and unbalancing have severe influence on control of various applications such as power quality devices, distributed generation systems, power converter devices, electric vehicle chargers and electric motors. Orthogonal $$\hbox {d}{-}\hbox {q}$$ signals are significantly a part of controller for these applications. This paper proposes a new synchronization method based on integration average filter (AF) into conventional phase locked loop (PLL) in order to attenuate negative effect of voltage harmonics and unbalanced on orthogonal $$\hbox {d}{-}\hbox {q}$$ signals for controller. Although some advanced techniques in the literature ensure good performances, uses of multiple filters reduce dynamic response and suffer from computational burden. The proposed improved AF-PLL has simple structure and implementation. It provides fast phase detection, fast dynamic response and removes ripple errors of voltage unbalance and harmonics. The performance of the filter-based PLL is evaluated in terms of balanced, unbalanced condition and harmonics distortion. The effectiveness and reliability of the proposed AF-PLL are demonstrated and discussed by means of comparative conventional PLL and advanced PLL in the literature. PSCAD/EMTDC is used for simulation and examination of all PLLs.

A New PLL Simulation Validation for Three-phase Grid under Heavy Distorted Conditions

The precision of phase-locked loop (PLL) has a direct effect on the output performance for three-phase grid-connected inverter or three-phase active PFC. In this paper, a new three-phase digital closed-loop phase-locked algorithm is proposed on the basis of synchronous reference frame transformation. Synchronous simulation of the PLL techniques is a good choice even if the polluted three-phase grid such as the harmonics, phase jump and unbalance. Finally, MATLAB digital simulation results prove that the proposed PLL can fast and accurately track the positive sequence fundamental components of three-phase grid voltage.

Recursive PLL based on the Measurement and Processing of Time

1 Abstract—This paper describes one recursive model of the Phase Locked Loop (PLL) of the second order based on the measurement and processing of the time difference between the input and output periods. The stability and the other conditions, under which the described system can have the properties of a PLL, are investigated using the Z transform analyses. Computer simulation of PLL is introduced in order to give better insight into the PLL characteristics and to confirm the mathematical analyses too. Made analysis shows that PLL is suitable for the wide range of applications. For the corresponding system parameters, PLL possesses the power noise rejection ability. For some other system parameters this PLL possesses the power tracking ability. It can also be used for the measurement of the period of the input signal in the noise environment. The oscilloscope picture of the input and output signals recorded on the realized PLL is presented.

The latency insertion method for simulations of phase-locked loops

In this paper, we present two methods for the simulations of phase-locked loops (PLL) based on the latency insertion method (LIM). First, we present a novel and simple behavioral model based simulation method that exploits the latency in the PLL formulation and utilizes a leapfrog time stepping discretization scheme to solve for the transient response of the PLL. Next, we apply LIM to the simulation of PLLs at the transistor level. Various PLL dynamic responses such as lock-in, pull-in and pull-out conditions are simulated and comparisons with analytical solutions are depicted when available. Results are also compared to traditional SPICE-based methods. Finally, a bottom-up behavioral simulation approach is illustrated by using LIM to generate individual models for the PLL components which are then used in an overall behavioral level simulation.

A Precise and High Speed Charge-Pump PLL Model Based on SystemC/SystemC-AMS

Abstract The Phase Locked Loop (PLL) has become an important part of electrical systems. When designing a PLL, an efficient and reliable simulation platform for system evaluation is needed. However, the closed loop simulation of a PLL is time consuming. To address this problem, in this paper, a new PLL model containing both digital and analog parts based on SystemC/SystemC-AMS (BETA version) is presented. Many imperfections such as Voltage Control Oscillator (VCO) noise or reference jitter are included in this model. By comparing with the Matlab model, the SystemC/SystemC-AMS model can dramatically reduce simulation time. Also, by comparing with Analog Devices ADI SimPLL simulation results, Cadence simulation results and real measurement results, the accuracy of the SystemC/SystemC-AMS model is demonstrated. The paper shows the feasibility of a unified design environment for mixed-signal modelling based on SystemC/SystemC-AMS in order to reduce the cost and design time of electrical systems.

Theoretical Modeling and Simulation of Phase-Locked Loop (PLL) for Clock Data Recovery (CDR)

Modern communication and computer systems require rapid (Gbps), efficient and large bandwidth data transfers. Agressive scaling of digital integrated systems allow buses and communication controller circuits to be integrated with the microprocessor on the same chip. The Peripheral Component Interconnect Express (PCIe) protocol handles all communcation between the central processing unit (CPU) and hardware devices. PCIe buses require efficient clock data recovery circuits (CDR) to recover clock signals embedded in data during transmission. This paper describes the theoretical modeling and simulation of a phase-locked loop (PLL) used in a CDR circuit. A simple PLL architecture for a 5 GHz CDR circuit is proposed and elaborated in this work. Simulations were carried out using a Hardware Description Language, Verilog-AMS. The effect of jitter on the proposed design is also simulated and evaluated in this work. It was found that the proposed design is robust against both input and VCO jitter.ABSTRAK: Sistem komunikasi dan komputer moden memerlukan pemindahan data yang cekap (Gbps), dan bandwidth yang besar. Pengecilan agresif menggunakan teknik sistem digital bersepadu membenarkan bas dan litar pengawal komunikasi disatukan dengan mikroprocessor dalam cip yang sama. Protokol persisian komponen sambung tara ekspres (PCIe) mengendalikan semua komunikasi antara unit pemprosesan pusat (CPU) dan peranti perkakasan. Bas PCIe memerlukan litar jam pemulihan data (CDR) yang cekap untuk mendapatkan kembali isyarat jam yang tertanam dalam data semasa transmisi. Karya ini menerangkan teori pemodelan dan simulasi gelung fasa terkunci (PLL) untuk CDR. Rekabentuk 5 GHz PLL yang mudah telah dicadangkan dalm kertas kerja ini. Simulasi telah dijalankan menggunakan perisian verilog-AMS. Simulasi mengunnakan kesan ketar dalam reka bentuk yang dicadangkan telah dinilai. Reka bentuk yang dicadangkan terbukti teguh mengatasi ganguan ketar di input dan VCO.KEY WORDS: phase-locked loop (PLL); jitter; phase detector; low-pass filter; voltage-controlled oscillator