The latency insertion method for simulations of phase-locked loops

Abstract

In this paper, we present two methods for the simulations of phase-locked loops (PLL) based on the latency insertion method (LIM). First, we present a novel and simple behavioral model based simulation method that exploits the latency in the PLL formulation and utilizes a leapfrog time stepping discretization scheme to solve for the transient response of the PLL. Next, we apply LIM to the simulation of PLLs at the transistor level. Various PLL dynamic responses such as lock-in, pull-in and pull-out conditions are simulated and comparisons with analytical solutions are depicted when available. Results are also compared to traditional SPICE-based methods. Finally, a bottom-up behavioral simulation approach is illustrated by using LIM to generate individual models for the PLL components which are then used in an overall behavioral level simulation.