Simulation Of MOSFETs Research Articles

Effect of specularity parameter and convective coefficient on heat transport in semiconductor devices based on mesoscopic method

The effects of thermal behavior on nanoscale Metal Oxide Semiconductor Field Effect Transistor (nano-MOSFET) are still being studied by the semiconductor industry. This study investigates the heat diffusion inside double-gate (DG) and nano-conventional MOSFETs. Simulations of conventional and DG MOSFET are carried out using mesoscopic model lattice Boltzmann method (LBM) coupled with specularity parameter and convective heat transfer coefficient. The simulation results show that the specularity parameter and convective heat transfer term have important role to reduce hotspots in nano-devices. Temperature decreases when the specularity parameter and convective term increase. The temperature reaches 326.76 K for p = 0.1 while for p = 0.4 estimated 320.79 K at the same Rth−1=1010 W/(m2⋅K) in traditional device at t = 30 ps whereas the temperature in the double gate transistors reached 326.28 K and 321.48 K for p = 0.4 and 0.8, respectively. In addition, it is found that the conventional device compared with the double gate device is more heat stability.

Monte Carlo study of carrier transport in two-dimensional transition metal dichalcogenides: high-field characteristics and MOSFET simulation

Monte Carlo study of carrier transport in two-dimensional transition metal dichalcogenides: high-field characteristics and MOSFET simulation

Numerical Simulation of Electro-Thermal Properties in FDSOI MOSFETs Down to Deep Cryogenic Temperatures

An original reformulation of the thermopower S, heat conductivity K and heat capacitance C in bulk silicon for electrons and phonons is first proposed. Closed-form analytical approximations for these coefficients as a function of Fermi level, temperature and/or carrier concentration are developed for implementation in TCAD simulation. These analytical expressions for S, K and C have been employed to simulate the electro-thermal properties of a FDSOI (Fully depleted silicon on insulator) MOSFET versus front gate voltage from room down to very low temperature. The obtained results allow discriminating the electron and phonon contributions to the whole properties. These analyses could be very useful to further performing TCAD simulations of FDSOI MOSFETs down to very low temperature for full assessment of electro-thermal performances.

Integrated DC - DC converter design methodology for design cycle speed up

A novel design methodology, enabling extreme design cycle time speed up of DC - DC power converters, is developed. The concept is based on providing high accuracy post-layout RC parasitics aware results, by replacing complicated large RC netlists with small signal approximation models. Scattering parameters analysis is adopted for “on the fly” performance simulation of the power MOSFET switches' routings, which act as large passive linear networks. The RC parasitics aware back end of line (BEOL) S-parameter model is extracted and seamlessly integrated into the schematic testbench, considering the actual circuit as a black box and therefore actively cutting down the design's netlist size to minimum values. Thus, the DC – DC converter performance degradation, that previously could not be simulated, now is accurately predicted and evaluated while the respective simulation time and the number of design iterations needed from layout (physical design) to the schematic and vice versa, are minimized. The proposed methodology is validated using an Integrated Pulse Width Modulation controlled DC - DC converter product vehicle, for light energy harvesting applications, designed, simulated and fabricated in a 0.18 μm CMOS standard process. Experimental results confirm the accuracy and design cycle speed up effectiveness of the proposed novel IC power converter design methodology.

Proposal and Simulation of Ga2O3MOSFET With PN Heterojunction Structure for High-Performance E-Mode Operation

Proposal and Simulation of Ga₂O₃MOSFET With PN Heterojunction Structure for High-Performance E-Mode Operation

Analytical Exploration and Simulation of Dual-Material Gate Macaroni Channel MOSFET biosensor using dielectric-modulation technique

The paper presents extensive analytical modeling and simulation of a novel Dual-Material Gate Macaroni-Channel MOSFET to act as a biosensor for detection of neutral as well as charged biomolecules using dielectric modulation approach. Dielectric modulation in a MOSFET device is the alteration in the dielectric constant in the gate dielectric region of the device. Presence of biomolecules (in a nanogap etched under the gate of the projected device) having different dielectric constants impact the gate capacitance that in turn affects the device features such as potential, threshold voltage, drain current which undergo considerable shift in presence of biomolecules. Detailed Sensitivity analysis based on threshold voltage shift for different types of biomolecule allows suitable detection of biomolecule type. Suitable selection of device outer radius allows significant suppression of some major Short channel effects such as threshold voltage reduction, reduced subthreshold swing enabling superior device performance. Finally, comparative sensitivity analysis of the proposed device with its full channel Cylindrical Gate-all-around counterpart having same channel thickness exhibits better sensitivity capability of the proposed device for both neutral and charged biomolecule. Analytical results are substantiated using Atlas simulation outputs.

Comparative Study of Double Gate and Silicon on Insulator MOSFET by Varying Device Parameters

A comparative study of the single gate MOSFET (SG MOSFET), double-gate MOSFET (DG MOSFET) and silicon-on-insulator MOSFET (SOI MOSFET) is done using MOSFET simulation tool. Device simulation is done by varying different physical parameters of the device structure such as oxide thickness, channel length, temperature and different gate electrodes. Contour plots of SOI and DG MOSFET for electron concentration and potential at initial and final bias are simulated. The drain current vs gate voltage (Id-Vg) characteristics performance simulations show that DG MOSFET is better than SOI MOSFET for different oxide thickness and channel length. It was further noticed that with an increase in the oxide thickness, drain current decreases for DG and SOI MOSFETs. When oxide thickness is reduced from 10 to 7 nm keeping all other parameters same, in DG MOSFET drain current increased by 49.49 % and in SOI MOSFET drain current increased by 66.6 %. When channel length is reduced from 80 to 75 nm in DG MOSFET drain current increased by 1.35 % and in SOI MOSFET drain current increased by 2 %. The performance simulations show that aluminium (Al) gate electrode is better than n+ poly silicon (Si) and tungsten (W) for every MOSFET devices. With respect to aluminium gate electrode in DG MOSFET, for n+ poly Si and tungsten, drain current decreased by 3.89 and 30.5 %, respectively and in SOI MOSFET, for n+ poly Si and tungsten, drain current decreased by 3.84 and 34.61 %, respectively.
 HIGHLIGHTS
 
 Comparative study of Double Gate and Silicon on Insulator MOSFET
 Simulation of DG and SOI MOSFET using MOSFET simulation tool on nanohub.org
 Performance analysis of DG and SOI MOSFET by varying different physical parameters like oxide thickness, channel length, temperature and gate electrodes
 Drain current vs gate voltage (Id-Vg) characteristics performance simulation of DG and SOI MOSFET
 Contour plot for electron concentration and potential
 
 GRAPHICAL ABSTRACT

Hybrid Data-Driven Modeling Methodology for Fast and Accurate Transient Simulation of SiC MOSFETs

To enable fast and accurate models of SiC MOSFETs for transient simulation, a hybrid data-driven modeling methodology of SiC MOSFETs is proposed. Unlike conventional modeling methods that are based on complex nonlinear equations, data-driven artificial neural networks (ANNs) are used in this article. For model accuracy, the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$I$</tex-math></inline-formula> – <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$V$</tex-math></inline-formula> characteristics are measured in the whole operation region to train the ANN. The ANN model is then combined with behavior-based equations to model the cutoff region and to avoid overfitting the ANN. In addition, the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$C$</tex-math></inline-formula> – <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$V$</tex-math></inline-formula> characteristics are modeled by ANNs with a logarithmic scale for accuracy. The proposed model is implemented and simulated in SPICE simulator SIMetrix. The simulation results are compared with experimental results from a double pulse tester to validate the proposed modeling methodology. The model is also compared with the Angelov model created by the Keysight MOSFET modeling software. The comparison results show that the proposed model is more accurate than the Angelov model. Besides, when compared to the Angelov model, the proposed model requires 30% less computation time when simulating a double pulse tester. In addition, the proposed modeling method also has better adaptability to model different types of SiC MOSFETs.

Nano Device Simulator—A Practical Subband-BTE Solver for Path-Finding and DTCO

We present an in-depth discussion on the subband Boltzmann transport (SBTE) methodology, its evolution, and its application to the simulation of nanoscale MOSFETs. The evolution of the method is presented from the point of view of developing a commercial general-purpose SBTE solver, the GTS nano device simulator (NDS). We show a wide range of applications SBTE is suited for, including state-of-the-art nonplanar and well-established planar technologies. It is demonstrated how SBTE can be employed both as a path-finding tool and a fundamental component in a DTCO-flow.

Design and simulation of gallium nitride trench MOSFETs for applications with high lifetime demand

Design and simulation of gallium nitride trench MOSFETs for applications with high lifetime demand

TCAD modeling of bias temperature instabilities in SiC MOSFETs

TCAD simulations of SiC power MOSFETs have been performed to study the dependence of positive-bias temperature instability (PBTI) on temperature and electric field. The model used to describe the kinetics of the transition rates between neutral and charged traps is the extended Non-Radiative Multi Phonon (eNMP). Connections between oxide defect configurations at the interface with SiC substrate have been made. Validation against experiments is shown.

Transport process and energy loss of heavy ions in silicon carbide

Using the Monte Carlo method, the energy losses in silicon carbide of heavy ions with different linear energy transfers (LETs) are simulated and calculated. The simulation results show that the energy loss per unit depth of heavy ions in silicon carbide is affected by both the ion energy and the incident depth. Primary heavy ions and secondary electrons mainly cause energy loss, and the non-ionization energy loss only accounts for about 1% of the total energy loss. With the increase of LET, the initial angle and energy distribution of the secondary electrons become more and more concentrated. The peak position of the generated charge deposition is in the center of the heavy-ion track, and the distribution is linearly decreasing in Gaussian form in the direction perpendicular to the incident depth. In the californium source experiment of SiC MOSFET, when the drain voltage is 480 V, the device has a single event burnout, and the breakdown voltage of SiC MOSFET is less than 1 V after burnout has occurred. With the experimental results, we carry out the TCAD simulation of SiC MOSFET and obtain the electric field distribution inside the device under different drain voltages. The electric field parameters are used in the Monte Carlo simulation of SiC MOSFET with considering the metal layer. It is found in the Monte Carlo simulation that the greater the electric field of the epitaxial layer, the longer the path of heavy ions moving on the epitaxial layer is and the more the deposited energy, and that the secondary electrons are more likely to move in the direction of the electric field as the electric field increases, resulting in excessive energy deposition in local areas.

Modeling and Simulation of MOSFET (High-k Dielectric) Using Genetic Algorithms

Modeling and Simulation of MOSFET (High-k Dielectric) Using Genetic Algorithms

AN EXPERIMENTAL VERIFICATION OF NEW NON-QUASI-STATIC SMALL-SIGNAL MOSFET MODEL

This article presents the results of an experimental verification of the New Non-Quasi-Static (NQS) Small-Signal MOSFET Model proposed in [1,2]. This model is valid in all operating modes, from weak to strong inversion and from nonsaturation to saturation. For the purpose of verification test transistors with de-embedding, dummy structures in 0.35 m technology were designed. The procedure of de-embedding was based on the open-short [3] method, optimised for RF measurement up to 30 GHz. The results obtained have confirmed aplicability of the model for the small-signal MOSFET simulation.

Design and simulation of 3C-SiC vertical power MOSFETs

ABSTRACT This paper reports on the design and simulation of 3C-SiC low-doped drain power MOSFETs, including key parameters such as the avalanche impact ionisation model and its relation to the breakdown voltage, the doping dependence of the bulk mobility, and the relationship between the on-resistance and breakdown voltage. A set of MOSFETs with different blocking layer doping were designed while scaling the parasitic JFET. A stepped doping profile is used to minimise localised breakdown at the p-well/n-type drift layer interface. The characteristics of the MOSFETs were obtained using a commercially available 2D simulation program. 2D Simulation results show good agreement with 1D model of the on-state resistance and current-voltage characteristics. The deviation from the experimental data may be due to using different designs and or may be due to the presence of surface charges excluded from 2D simulations and 1D quadratic model. Simulation results indicate that, for the chosen material parameters, a 600 V, 3C-SiC MOSFET with a thinned substrate, containing a drift-layer of 7 μm and a blocking layer doping density of 1 × 1016 cm−3, can have an on-state resistance of 0.8 mΩ-cm2.

Developing 13-kV 4H-SiC MOSFETs: Significance of Implant Straggle, Channel Design, and MOS Process on Static Performance

13-kV 4H-SiC MOSFETs were successfully fabricated on a 125- $\mu \text{m}$ -thick epitaxial layer on 6-in, N+ SiC substrates. Both lateral and longitudinal straggles from the P-well implant were investigated to optimize the JFET width and thus to avoid channel pinching in the JFET region. Channel lengths and channel mobilities were varied to investigate the effect of channel portions in determining the ON-state resistance of the 13-kV MOSFETs. It was discovered that the low channel mobility limits the transconductance, such that the MOSFETs cannot offer full current at reasonable gate voltages ( ${V}_{\text {gs}} = \sim \,\,20$ V). Even in high voltage MOSFETs, it is essential to have a reasonably high channel mobility to reduce ON-state power loss. Therefore, channel design and process are also important aspects of high voltage devices. A superior blocking capability of 13.2 kV was demonstrated using a ring-based edge termination structure. It is important to note that the straggling effect due to ion implantations should also be taken into account when designing an edge termination structure. Static electrical characteristics, scanning electron microscope (SEM) imaging, secondary ion mass spectrometry (SIMS) analysis, and 2-D simulation of the 13-kV MOSFETs were employed to support this reasoning.

Threshold voltage and DIBL effect analysis and modeling for FD-SOI MOSFET with high k + SiO$_2$ gate

This study aims to propose a gate structure of high k + SiO$_2$ for a fully depleted silicon-on-Insulator (FD-SOI) MOSFET. We developed a two-dimensional model to calculate its subthreshold surface potential of the front gate, threshold voltage, and drain induced barrier lowering (DIBL) effect. Based on the structure and different dielectric permittivity of FD-SOI MOSFET, the MOSFET of the subthreshold state is divided into several distinct rectangular equivalent sources. Furthermore, two-dimensional (2D) boundary value problems of Poisson and Laplace equations are built on the polygon region. Then, we use the method of separation of variables and the eigenfunction expansion to solve the 2D boundary value problems, and obtained their 2D solutions. Computational results show that the high k + SiO$_2$ gate can effectively suppress the degradation of FD-SOI MOSFET threshold voltage, the aggravation of DIBL effect, and the FIBL effect, which are caused by the dielectric permittivity of high k. Since the equations of the model are linear equations, their computational cost is minimal so that the model can be used for not only modeling and simulation of FD-SOI MOSFETs but also as a device model of circuit simulators.

2D analytical modeling and simulation of dual material DG MOSFET for biosensing application

In the recent times, the performance of MOSFET in the nanoscaled region attains improvisations through several alternative device structures. Amongst many advanced MOSFET structures, the Double Gate (DG) MOSFET is one such structure which mitigates short channel effects because of its excellent scalability. Among the various structures, FET- based biosensors have shown an accelerated growth recently. Even though many analytical models are available for the Dual Material DG (DMDG) MOSFET structures, this work endeavours to introduce an analytical modeling of nanocavity embedded DMDG structure for the first time. The expression for surface potential is obtained by solving the 2-D Poisson’s equation using a parabolic-potential approach. The threshold voltage is determined from the minimum surface potential model. Sensitivity is computed in terms of relative change in the threshold voltage and it is derived using the model. The influence of various device geometrical parameters like length and thickness of the nanocavity on the sensitivity has been investigated. Further, a comparison of the sensitivity of DG MOSFET and DMDG MOSFET has also been made and the derived results are validated against TCAD simulation results.

The backward Monte Carlo method for semiconductor device simulation

A backward Monte Carlo method for the numerical solution of the semiconductor Boltzmann equation is presented. The method is particularly suited to simulate rare events. The general theory of the backward Monte Carlo method is described, and several estimators for the contact current are derived from that theory. The transition probabilities for the construction of the backward trajectories are chosen so as to satisfy the principle of detailed balance. This property guarantees stability of the numerical method and allows for a clear physical interpretation of the estimators. A symmetric sampling method which generates wave vectors always in pairs symmetric to the origin can be shown to yield zero current exactly as thermal equilibrium is approached. The properties of the different estimators are evaluated by simulation of an n-channel MOSFET. Quantities varying over many orders of magnitude can be resolved with ease. Such quantities are the drain current in the sub-threshold region, the high-energy tail of the carrier distribution function, and the so-called acceleration integral which varies over 30 orders in the example shown.

Investigation of the Universal Mobility of SiC MOSFETs Using Wet Oxide Insulators on Carbon Face With Low Interface State Density

The universal mobility of SiC MOSFETs has been investigated. SiC MOSFETs with the gate oxide formed by wet oxidation have been fabricated on 4H-SiC ( $000\overline {\textsf {1}}$ ) substrates to reduce Coulomb scattering sources. In order to suppress charge trapping in the gate oxide during measurement, surface carrier concentration ( ${N}_{s}$ ), and channel current have been evaluated from the transient characteristic of source current and drain current under the application of pulse gate bias. To eliminate the influence of charge trapping in interface states, the concentration of electrons trapped in interface states has been estimated and subtracted from ${N}_{s}$ . Effective channel mobility ( $\mu _{\textsf {eff}}$ ) and effective electric fields ( ${E}_{\textsf {eff}}$ ) have been calculated from the ${N}_{\textsf {s}}$ and channel current. The substrate impurity concentration ( ${N}_{A}$ ) and substrate bias ( ${V}_{b}$ ) dependence of $\mu _{\textsf {eff}}$ – ${E}_{\textsf {eff}}$ characteristics have been investigated, and, as a result, it has been confirmed that $\mu _{\textsf {eff}}$ of SiC MOSFETs shows a universal characteristic as a function of ${E}_{\textsf {eff}}$ at high ${E}_{\textsf {eff}}$ , independent of ${N}_{\textsf {A}}$ and ${V}_{\textsf {b}}$ . In addition, we have investigated the temperature dependence of this universal mobility in the range of 223–423 K, and formulated the result in a simple model. This result leads to a better understanding of electron transport properties in SiC inversion layers and the improvement of the accuracy of device and circuit simulations of SiC MOSFETs.