Design and simulation of 3C-SiC vertical power MOSFETs

Abstract

ABSTRACT This paper reports on the design and simulation of 3C-SiC low-doped drain power MOSFETs, including key parameters such as the avalanche impact ionisation model and its relation to the breakdown voltage, the doping dependence of the bulk mobility, and the relationship between the on-resistance and breakdown voltage. A set of MOSFETs with different blocking layer doping were designed while scaling the parasitic JFET. A stepped doping profile is used to minimise localised breakdown at the p-well/n-type drift layer interface. The characteristics of the MOSFETs were obtained using a commercially available 2D simulation program. 2D Simulation results show good agreement with 1D model of the on-state resistance and current-voltage characteristics. The deviation from the experimental data may be due to using different designs and or may be due to the presence of surface charges excluded from 2D simulations and 1D quadratic model. Simulation results indicate that, for the chosen material parameters, a 600 V, 3C-SiC MOSFET with a thinned substrate, containing a drift-layer of 7 μm and a blocking layer doping density of 1 × 1016 cm−3, can have an on-state resistance of 0.8 mΩ-cm2.