Current overshoot during forming/SET of RRAM devices is frequently considered one of the key factors contributing to variation of the formed filament [1,2,4,5]. It is generally believed that to minimize variation, the current overshoot should be controlled by minimizing the device parasitics [2,4,5]. On the other hand, there are reports suggesting that RRAM requires an optimum energy to form a robust filament [3,6,7]. In this paper, we show that for RRAM systems with compliance control, such as 1T-1R, this forming energy is linked to the current overshoot which in turn is linked to capacitance. In other words, blindly minimizing parasitics is a poor strategy. Instead, the device should be engineered for optimum (not minimum) parasitics. Previously, it has been shown that the duration of the overshoot current is determined by the parasitic capacitance [1]. A surprising consequence is that even with a long programming pulse, the actual current that flows through the RRAM can become very short when current compliance is used. For devices with extremely low parasitics, such as in actual production devices, it can lead to an effective programming pulse duration that is picoseconds or less. This unexpected ultra-short effective programming pulse means that an unexpectedly low amount of energy is dissipated into the filament and can lead to poor retention and endurance. Thus, it suggests that the common idea of minimizing the parasitics is counter-productive. In order to verify, high speed 1T-1R measurements were done with the experimental set up shown in Fig. 1. Five similar sized crossbar devices with different drain capacitances were measured. The details of the devices are given in Fig. 2. As shown in Fig. 1, we measure the current at the source side of the transistor by connecting it to the 50 Ω input of the oscilloscope (Fig. 3). This is not a direct measurement of the current going through the RRAM because only part of the charge of the parasitic capacitor flows through the transistor. The current paths are depicted in Fig. 4. Nevertheless, the measured current mirrors the current flowing through the RRAM and serves as a proxy. The current peaks (Fig. 3) for devices 1 to 3 decay in that order. These devices have similar capacitance but the post forming resistance decreases by the same order. For devices 4 and 5, that do not have a probe pad connected to the drain, the capacitances are much lower and thus an extremely short current peak is seen for device 4 and almost no current peak is observed for device 5. The missing current peak is due to finite sampling resolution (12.5 ps) of the oscilloscope and the current pulse being very short. To verify, we compare the results with spice modeling as shown in Fig. 4, including reflections of the fast pulse due to inevitable impedance mismatch of the device (not designed for RF measurements) and with a resolution of 12.5 ps to match that of the oscilloscope. For the simulations, the RRAM device was modeled as a variable resistor with resistance changing linearly from 20 MΩ to about 6 kΩ. Good agreement between the spice simulations and the measured current is achieved, as shown in Fig. 5. The simulated current waveforms, with 12.5 ps sampling resolution for all 5 devices are shown in Fig. 6. The peak is noticeable for device 5. In Fig. 7 we focus only on device 5; the sampling resolution is changed to 2 ps and the peak is clearly recovered. The agreement between simulation and experiment confirms our model prediction that (1) no matter how low the parasitic component is, current overshoot exists; (2) the magnitude of the current overshoot is determined by the applied voltage and the RRAM resistance, not the parasitic capacitance; (3) the parasitic capacitance determines the duration of the current overshoot. Fig. 8 shows the simulated current overshoot for devices of the same Rform and forming voltage but different parasitic capacitance. Clearly, both (2) and (3) affects the energy dissipated into the RRAM filament. With a targeted resistance, the only control available is the applied voltage and parasitic capacitance. When the parasitic capacitance is very low, the voltage must increase to provide optimum energy for a stable RRAM with long retention times and good endurance. However, high voltage tends to amplify the stochastic nature of the filament and can only go so far before losing control. Thus, the main avenue left for optimizing RRAM is to optimize the parasitics instead of minimizing it – a major departure from common wisdom. Figure 1
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Jul 25, 2024
Chengwei Shen + 4
Open Access