SIMD Processor Array Research Articles

Using Ella as a Design Tool

An overview of the ELLA system is given, followed by a description of how it has been used as an architectural tool to develop packet-switching networks for SIMD processor arrays. Finally, the merits and drawbacks of ELLA are discussed, with a summary on current trends in automated design.

Incremental Polygon Rendering on a SIMD Processor Array

AbstractWe demonstrate how both area coherence and parallelism can be exploited in order to speed up rendering operations on a SIMD square array of processors. Our algorithms take advantage of the method of differences, in order to incrementally compute the values of a linear polynomial function at discrete intervals and thus implement area rendering operations efficiently. We discuss how filling of convex polygons, hidden surface elimination and smooth shading can be implemented on an N × N processor array that supports planar arithmetic, that is, arithmetic operations performed on N × N matrices in parallel for all matrix elements. A major attraction of the method we present is that it is based on a SIMD processor array; such machines are now recognised as highly general purpose given the wide range of applications successfully implemented on them.

Searching and clustering of databases using the ICL Distributed Array Processor

The ICL Distributed Array Processor (DAP) is an SIMD array processor containing a large, 2-D array of bit serial processing elements. The architecture of the DAP makes it well suited to data processing applications where searching operations must be carried out on large numbers of data records. This paper discusses the use of the DAP for two such applications, these being the scanning of serial text files and the clustering of a range of types of database. The processing efficiency of the DAP, when compared with a serial processor, is greatest when fixed length records are processed.

Parallel matching and reconstruction algorithms in computer vision

Parallel implementations of a number of computer vision algorithms for visual reconstruction and matching are described. The algorithms chosen range in complexity from those requiring only image correlation and other simple operations to more sophisticated iterative algorithms involving relaxation, simulated annealing and graduated non-convexity. In each case the algorithms are implemented in parallel by mapping the images directly onto an SIMD processor array. Brief descriptions of the algorithms are given together with sample results and timings for their implementation on a 64 × 64 ICL DAP.

Necessary and Sufficient Conditions for the Existence of Local Matrix Decompositions

Let $D = ( V,E )$ be a directed graph with n vertices. We define the notion of a local matrix with respect to D and we show that every $n \times n$ matrix, over the real or complex numbers, can be factored into a product of local matrices with respect to D if and only if D is strongly connected and contains all loops. We discuss the significance of this result with respect to parallel computation of linear transforms on SIMD processor arrays. We observe that the result can be used to associate with certain irreducible $n \times n$ matrices a generating set of the semigroup of all $n \times n$ matrices under matrix multiplication.

A kernel-independent, pipelined architecture for real-time 2-D convolution

Existing architectures for 2-D convolution suffer from such drawbacks as inflexibility with respect to image and/or kernel sizes (systolic arrays) or data distribution and collection overhead (SIMD processor arrays). This paper introduces a pipelined architecture that maps different sizes and shapes of kernels on a fixed size array of computing elements using a single pass of the input data. It is shown that the array can be operated at its highest throughout for any kernel size. Interfacing this architecture with the host requires receiving and outputting data in a simple raster-scan fashion.

Software and hardware techniques for string searching in serial document databases

This paper considers the use of text signatures and of parallel computer hardware to increase the efficiency of text scanning in serial document files. After a review of software and hardware techniques for text scanning, the characteristics of text signature systems for document retrieval are discussed, in particular the relationship between text signature length and both the efficiency and the effectiveness of searching. A parallel pattern matching algorithm is then described for use with the ICL Distributed Array Processor, a highly parallel SIMD array processor. The efficiency of this algorithm is compared with that of the Aho-Corasick pattern matching algorithm when implemented on a conventional minicomputer. Microprocessor-based multiprocessing networks are becoming widely available as a means of implementing MIMD parallelism. Experiments with the Boyer-Moore pattern matching algorithm on a network of INMOS transputers demonstrate near-linear speed-ups for networks containing up to 11 transputers.

Parallel Algorithms for Image Template Matching on Hypercube SIMD Computers

This correspondence presents several parallel algorithms for image template matching on an SIMD array processor with a hypercube interconnection network. For an N by N image and an M by M window, the time complexity is reduced from O(N2M2) for the serial algorithm to O(M2/K2 + M * log2 N/K + log2 N * log2 K) for the N2K2-PE system (1 ¿ K ¿ M), or to O(N2M2/L2) for the L2-PE system (L ¿ N). With efficient use of the inter-PE communication network, each PE requires only a small local memory, many unnecessary data transmissions are eliminated, and the time complexity is greatly reduced.

A parallel approach to the picture restoration algorithm of Geman and Geman on an SIMD machine

This paper considers how the image restoration technique of Geman and Geman, which involves searching for the maximum a posteriori distribution of an image modelled as bounded Markov random fields using simulated annealing, can be approximated on a parallel SIMD processor array, the ICL Distributed Array Processor (DAP). For the version implemented, the potential speed-up over an equivalent serial processor is equal to half the number of processors in the array, or 2048 for the 64×64 DAP. The time taken by the DAP for one updating cycle is about 30 ms, and the typical complete picture restoration consisting of 1000 annealing cycles takes around 30 s. A method of increasing the efficiency of the present algorithm is suggested and the possibility of making the algorithm work with several frames of data collected over time is discussed.

A Class of Array Architectures for Hardware Grid Routers

Special-purpose hardware architectures have been recently proposed for solving a number of increasingly complex design automation problems. This paper proposes a class of two-dimensional SIMD array processors--the IAP architectures for implementation of grid routing algorithms. The major advantages of the IAP machines are, completely modular designs which are not pin-limited regardless of array size, and the ability to find the lowest cost route for a net, in time which is a linear function of the length of that route. A number of new procedures for parallel routing (simultaneous routing of k nets) are introduced, which take advantage of the linear time complexity of the IAP architectures. An analysis is presented of the time complexities of these procedures and examples are presented to exhibit their applicability.

Structure-from-motion algorithms for computer vision on an SIMD architecture

Algorithms for interpreting the motion of edge features in an image sequence in terms of the position, orientation and motion of a planar visible surface facet have been developed and implemented on an SIMD processor array. The underlying theory of the interpretation based on a simultaneous solution of the structure-from-motion and aperture problems is briefly reviewed and it is explained how the solution can be implemented very simply and efficiently on an SIMD processor array. Test calculations were carried out on the ICL DAP at Queen Mary College to illustrate the implementation and to show that, for an ideal 1: 1 mapping of the image pixels onto the processor array, the algorithms run at speeds that are nearly compatible with real time video frame rates.