SIMD Mesh Research Articles

An efficient sorting algorithm on the multi-mesh network

The shear-sort algorithm on an SIMD mesh model requires 4/spl radic/N+o(/spl radic/N) time for sorting N elements arranged on a /spl radic/N/spl times//spl radic/N mesh. In this paper, we present an algorithm for sorting N elements in time O(N/sup 1/4/) on an SIMD multi-mesh architecture, thereby significantly improving the order of the time complexity. The multi-mesh architecture is built around n/sup 2/ blocks, where each block is an n/spl times/n mesh with n=N/sup 1/4/, so that each processor will uniformly have four neighbors in the final topology.

Parallel transitive closure computation in relational databases

The transitive closure operation is an important extension to relational algebra. Because of its high computation cost, it is of great interest to design efficient parallel algorithms for computing the transitive closure in relational database systems. In this paper, we present a new algorithm to compute transitive closures on SIMD meshes based on relational algebra operations. Double-hash distribution is used to avoid rehashing new tuples for the next join phase. There presently exists no extra step for the redistribution of these tuples. Possible redundant computation between different join phases has been prevented without using global operations. As only regular linear communication occurs on the mesh, and the workload is fully distributed, a speedup of O( n × n) has been achieved, where n × n is the size of mesh. Therefore, this algorithm is an optimal parallel version of the transitive closure algorithms based on relational algebra operations on SIMD meshes.

QUADTREE ALGORITHMS FOR TEMPLATE MATCHING ON MESH CONNECTED COMPUTER

We present four algorithms to perform template matching of an N×N image with an M×M template. The first algorithm is sequential, and the others are based on a SIMD mesh connected computer with N×N processors. In the first three algorithms, both the image and the template are represented by quadtrees, whereas in the last one, the template is represented by a quadtree, and the image is represented by a matrix. The time complexities of the four algorithms are respectively upper-bounded by α1N2M2, α2N+β2M2, α3N+β3M2, and β4M2, where α1, α2, β2, α3, β3, and β4 are constants.

A simplified design strategy for mapping image processing algorithms on a SIMD torus

It is proposed to enhance and simplify the programming of a two dimensional (2-D) torus (and mesh) connected SIMD array of simple processing elements (PEs) by introducing two dedicated communication registers in each PE. A new SIMD algorithm to transpose a matrix using only two buffers at each PE is described. A method is proposed to effectively realize large number of arbitrary, one-to-one, personalized, and concurrent communication between the PEs, by suitably repeating the matrix transpose algorithm. Implementation of several image processing tasks of shift-variant nature, such as hough transform, histogram, median filters, which involve such communication, is enhanced by this approach. The dynamic behavior of such a SIMD implementation is data independent, unlike the ones that employ greedy methods for handling the overall communication. This feature facilitates coordinated use of several independently operating SIMD meshes in a newly emerging computer vision paradigm known as multiview image-sequence analysis (MVISA) for 3-D perception of unstructured dynamic scenes.

A Fast Algorithm for Image Component Labeling with Local Operators on Mesh Connected Computers

A new parallel algorithm for image component labeling with local operators on SIMD mesh connected computers is presented. This algorithm provides a positive answer to the open question of whether there exists an O(n)-time and O(log n)-space local labeling algorithm on SIMD mesh connected computers. The algorithm uses a pipeline mechanism with stack-like data structures to achieve the lower bound of O(n) in time complexity and O(log n) in space complexity. Additionally, the algorithm has very small multiplicative constants in its complexities by using local parallel-shrink and label-propagate operations.

Practical Algorithms for Online Routing on Fixed and Reconfigurable Meshes

The critical problem in creating practical online SIMD mesh routing algorithms is to minimize both the number of communication steps and the size and complexity of the queues required at each PE (processing element). Currently, the best available algorithms for likely array sizes require 16n routing steps with queue size 1; if priority queues of size 2q − 1 are allowed, the number of routing steps required is reduced to 14n/q + 2n. We present an algorithm (the MGRA), based on wormhole routing, that has routed a large number of communication patterns (all patterns tried besides a synthetically constructed worst case) in 5n routing steps with a FIFO queue of size 2. We also show that the MGRA can be modified for meshes with broadcast buses and reconfigurable broadcast buses to route in a similar number of routing steps but with a queue size of 1. A second algorithm (the CGRA) uses reconfigurable broadcast buses in implementing cut-through routing. Using the CGRA, sparse patterns are routed in a small constant number of communication steps. We prove that the MGRA has bad worst case performance, but also show that a randomizing preprocessing step can improve the predictability of the original result. Finally, we show how performance scales with changing inter- and intra-PE path widths.

The scalability of FFT on parallel computers

The authors present the scalability analysis of a parallel fast Fourier transform (FFT) algorithm on mesh and hypercube connected multicomputers using the isoefficiency metric. The isoefficiency function of an algorithm architecture combination is defined as the rate at which the problem size should grow with the number of processors to maintain a fixed efficiency. It is shown that it is more cost-effective to implement the FFT algorithm on a hypercube rather than a mesh despite the fact that large scale meshes are cheaper to construct than large hypercubes. Although the scope of this work is limited to the Cooley-Tukey FFT algorithm on a few classes of architectures, the methodology can be used to study the performance of various FFT algorithms on a variety of architectures such as SIMD hypercube and mesh architectures and shared memory architecture.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Program compression on the instruction systolic array

Large-scale mesh-connected networks need to be made flexibly and yet efficiently programmable. To meet this need, this paper describes various approaches for program compression for the Instruction Systolic Array (ISA), a mesh model well suited to large-scale VLSI implementation. The implementations of these approaches match the (systolic) mesh's suitability for VLSI, have a modest area overhead and can significantly improve the ISA's overall performance, reduce the ISA system's overall hardware costs and, in the case of microprogramming, even improve flexibility. These techniques can also be applied to the less flexible SIMD mesh and the more flexible MIMD mesh. However, since they mitigate the ISA's chief relative disadvantages over the SIMD mesh model, they considerably reduce the attractiveness of the SIMD mesh as a fine-grained mesh model.

Orthogonal multiprocessor sharing memory with an enhanced mesh for integrated image understanding

This paper proposes a new parallel architecture, which has the potential to support low-level image processing as well as intermediate and high-level vision analysis tasks efficiently. The integrated architecture consists of an SIMD mesh of processors enhanced with multiple broadcast buses, and MIMD multiprocessor with orthogonal access buses, and a two-dimensional shared memory array. Low-level image processing is performed on the mesh processor, while intermediate and high-level vision analysis is performed on the orthogonal multiprocessor. The interaction between the two levels is supported by a common shared memory. Concurrent computations and I/O are made possible by partitioning the memory into disjoint spaces so that each processor system can access a different memory space. To illustrate the power of such a two-level system, we present efficient parallel algorithms for a variety of problems from low-level image processing to high-level vision. Representative problems include matrix based computations, histogramming and key counting operations, image component labeling, pyramid computations, Hough transform, pattern clustering, and scene labeling. Through computational complexity analysis, we show that the integrated architecture meets the processing requirements of most image understanding tasks.

Convolution on mesh connected multicomputers

An efficient parallel algorithm is presented for convolution on a mesh-connected computer with wraparound. The algorithm does not require a broadcast feature for data values, as assumed by previously proposed algorithms. As a result, the algorithm is applicable to both SIMD and MIMD meshes. For an N*N image and a M*M template, the previous algorithms take O(M/sup 2/q) time on an N*N mesh-connected multicomputer (q is the number of bits in each entry of the convolution matrix). The algorithms have complexity O(M/sup 2/r), where r=max (number of bits in an image entry, number of bits in a template entry). In addition to not requiring a broadcast capability, these algorithms are faster for binary images. >

A New Parallel Sorting Algorithm and its Efficient VLSI Implementation

In this paper we develop a new parallel algorithm for sorting which has a time complexity of O(log n) and requires n2/log n processors. The algorithm can be readily mapped on an SIMD mesh connected array of processors which has all the features of efficient VLSI implementation. The corresponding hardware algorithm maintains the O(Log n) execution time and has a low O(n) interprocessor communication time.

Parallel shape coding on a SIMD architecture

This paper presents a parallel shape analysis by simultaneous merging of elementary features detected through calculation of the number of objects within neighbouring windows. The parallel algorithm can be embedded on a SIMD mesh architecture. Elementary image features are detected inside partly overlapping windows fixed in the image plane. Each window's contents are processed by a separate processing element (PE). Two neighbouring elementary feature elements are merged by adjacent PEs, and the joined feature chunks are merged in the next step by every 2 2th PE possessing the same feature. Feature ends are propagated across N = 2 n PEs in each nth parallel step toward opposite edges of the mesh array of PEs. The shape coding is completed if all the feature limits (e.g. edges) meet together on one PE. The approach has the property of mapping an image fragment directly into words and phrases.

Connected component labeling of binary images on a mesh connected massively parallel processor

An algorithm for connected component labeling of binary patterns using SIMD mesh connected computers is presented. The algorithm consists of three major steps: identifying exactly one point (seed point) within each connected component (region), assigning a unique label to each seed point, and expanding the labels to fill all pixels in the respective regions. Two approaches are given for identifying seed points. The first approach is based on shrinking and the second on the iterative replacement of equivalent labels with local minima or maxima. The shrinking algorithm reduces simply connected regions into single pixels, but multiply connected regions form rings around the holes contained in the regions. A parallel algorithm is developed to break each such ring at a single point. The broken rings are then reduced to single pixels by reshrinking. With iterations consisting of shrinking, breaking rings, if any, and reshrinking, each pattern (of any complexity) is reduced to isolated points within itself. In the second approach every region pixel in the image is initially given a unique label equal to its address in the image. Every 3 × 3 neighborhood in the image is then examined in parallel to replace the central label with the maximum (or minimum) of the labels assigned to the set of region pixels in the neighborhood. This is done iteratively until there is no further change. The seed points are then the locations where the pixel addresses match their converged labels. A parallel sorting method is used for assigning a consecutive set of numbers as labels to the seed points. Parallel expansion up to the boundaries of the original patterns then completes the connected component labeling. The computational complexities of the algorithm are discussed.