Program compression on the instruction systolic array

Abstract

Large-scale mesh-connected networks need to be made flexibly and yet efficiently programmable. To meet this need, this paper describes various approaches for program compression for the Instruction Systolic Array (ISA), a mesh model well suited to large-scale VLSI implementation. The implementations of these approaches match the (systolic) mesh's suitability for VLSI, have a modest area overhead and can significantly improve the ISA's overall performance, reduce the ISA system's overall hardware costs and, in the case of microprogramming, even improve flexibility. These techniques can also be applied to the less flexible SIMD mesh and the more flexible MIMD mesh. However, since they mitigate the ISA's chief relative disadvantages over the SIMD mesh model, they considerably reduce the attractiveness of the SIMD mesh as a fine-grained mesh model.