Silicon Test Chips Research Articles

Design of an optimal pin-fin heat sink with air impingement cooling

A comparative investigation between experiments and numerical simulation is presented for turbulent air impingement flow on a square pin-fin heat sink. Experiments were conducted using an aluminum heat sink subjected to a uniform heat flux by using a silicon test chip. The numerical method incorporates the κ -ϵ turbulence model. The numerical results illustrate the complex pressure gradients within the fin array. The predicted thermal resistance of the heat sink agrees well with those obtained from experiments.This study illustrates the utility of numerical experiments in the design and optimization of heat sinks.

Implant-apertured and index-guided vertical-cavity surface-emitting lasers (I2-VCSELs)

We have fabricated vertical-cavity surface-emitting lasers (VCSELs) which, for the first time, effectively combine a shallow ion implanted aperture, for current confinement under a thin highly conducting lateral current injection layer, and an independent index guide for optical beam confinement (I/sup 2/-VCSELs). Both features are possible only because they are made before a top dielectric mirror is deposited and patterned, and are photolithographically defined for improved size reproducibility compared to oxide-confined designs. The devices emit near 980 nm and have optical power outputs of 1 mW at 2.5-mA input. The 12-VCSEL design also easily incorporates coplanar contacts allowing us to operate flip-chip bonded I/sup 2/-VCSEL's on silicon test chips at data rates of nearly 1 Gb/s.

A 25-kft, 768-kb/s CMOS analog front end for multiple-bit-rate DSL transceiver

A transceiver for multibit-rate digital subscriber loop is presented with up to 25-kft reach on using AWG 24 wire. An adjustable data rate from 160 to 768 kb/s is employed to achieve N/spl times/64 kb/s voice channel (N=2-12). The IC contains a 14-bit, 63 dual current sources multibit /spl Sigma//spl Delta/ digital-to-analog converter with "hopping" dynamic elements, a /spl Sigma//spl Delta/ analog-to-digital converter (ADC), and an on-chip high-swing nested Miller line driver; and for full duplex communication an integrated -30 dB rejection hybrid filter based on line and transformer parasitics matching. The concept has been tested using two sets of silicon test chips, one for symmetrical digital subscriber line (SDSL) and one for asymmetrical DSL (ADSL), on a line emulator with and without additive line noise for SDSL and ADSL rates (line driver external for ADSL with fourth-order multibit ADC for ADSL). In the analog front end, supply is 3 V for all the digital blocks, including the interface to the digital portion of the DSL, and 5 V for all the analog blocks. Power is 250 mW, with 12-mm/sup 2/ area. The transceiver can cover the full set of ANSI T1.601 basic rate ISDN (UkO-interface) loops while providing 2.5 times the throughput of existing U-interface transceivers. Nearly five times the throughput (768 kb/s) can be achieved even in the presence of worst case self-crosstalk. The additional performance is achieved by using a combination of coding, digital, and analog techniques.

Application of a CMOS current mode approach to on-chip current sensing in smart power circuits

A novel accurate CMOS current sensing circuit for the protection of smart power MOS switches, using the current mode approach is proposed. It has the advantage of not requiring any passive components and it is based on a CMOS current mode building block presenting a wide frequency bandwidth as well as temperature insensitivity. Two current sensing cells are necessary to detect open load, short-circuit and overcurrent situations. Detection is achieved by monitoring a small portion of the power switch current provided by a single-cell transistor (SENSEFET). The performance of these functions is analysed by electrical PSPICE simulations and experimental results obtained from a silicon test chip.

A dielectric surface coating technique to enhance boiling heat transfer from high power microelectronics

Two benign methods of generating surface microstructures, spraying and painting, provide pool boiling heat transfer enhancement. The methods do not require the target surface to be exposed to high stress environments, making them applicable to electronic component surfaces. The painted surface microstructures are applied to a rectangular, horizontally oriented surface, and provide up to a 85% reduction in incipient superheat. Between a 70 and 80% reduction in nucleate boiling superheats, and as much as a 100% increase in the maximum heat flux (critical heat flux-CHF), beyond that of the nontreated reference surface. The surface microstructures are also applied to a silicon test chip and tested at saturated and sub-cooled (45/spl deg/C) conditions using FC-72. At sub-cooled conditions, heat dissipation rates of 100 W/cm/sup 2/ were provided at junction temperatures of 85/spl deg/C, and the highest CHF observed was 159 W/cm/sup 2/, 224% higher than that from the untreated chip surface at saturated conditions. >

New RAM-bus Memory System with Interchip Optical Interconnection

A new optical RAM-bus (ORAM-bus) memory system has been proposed. The ORAM-bus memory has a number of optical interconnections to connect many memory chips. Data transfer using the guided optical interconnections is performed through the optical coupling flip-flop (OC-FF) circuit of the optical coupling sense amplifiers. The ORAM-bus memory test chips were fabricated using 2 µm complementary metal-oxide-semiconductor (CMOS) technology. The light-emitting diodes (LEDs) were successfully bonded onto the silicon test chips using the newly developed microbonding technology. The optical writing operation for ORAM-bus memory was demonstrated using the test chip.

Thermal shutdown CMOS circuits for smart power applications

Three maximum temperature detectors, based on CMOS/DMOS smart power technology, are presented. The first two circuits rely on the bandgap reference principle, while the third uses a self-biased bipolar transistor to measure the leakage current thermal variation of the reversed collector-base junction. The first two circuits were simulated with Pspice software, and a silicon test chip was produced for the third within the framework of the French Multi-Project Chip (MPC). The first thermal detector provides a constant voltage reference within ±20 ppm/°C over the −30 °C−+130 °C automotive temperature range. Simulations of the second circuit yield a 10·8 μA current with a thermal drift less than 12 nA from +10 °C to +130 °C. Experimental results of the third detector show that a good detection of the critical temperature, due to the exponential increase of the leakage current, can be achieved.

Hybrid Substrates for Power Electronic Applications: An Investigation of Thermal Resistance and Mechanical Stress

A new hybrid substrate technology for power electronic applications has been characterised by thermal resistance and mechanical stress measurements. The new substrate utilises thermal spray technology for deposition of dielectric layer and electrical conductors. The results are compared with the more established technology of alumina substrates with direct copper bonding (DCB) metallisation. Silicon test chips for thermal resistance and mechanical stress measurement were used for the characterisation. The experimental results were compared with finite element analysis and a reasonable agreement was found.

Short and long loop manufacturing feedback using a multisensor assembly test chip

A family of silicon test chips for use in making diagnostic measurements during electronics assembly has been developed. These assembly test chips (ATCs) contain sensors that measure a number of variables associated with assembled IC degradation, including the degree of integrated circuit (IC) corrosion, handling damage, electrostatic discharge threat, moisture or humidity, mechanical stress, mobile ion density, bond pad cratering, and high-speed logic degradation. The chips in the ATC family are intended to give manufacturing feedback in four ways: direct feedback in evaluation of an assembly manufacturing line in an objective, nonintrusive way; before and after comparisons on an assembly production line when an individual process, material, or piece of equipment has been changed; resident lifetime monitor for system package aging and ongoing reliability projection; and thermal, mechanical, DC electrical, and high-frequency mock-up evaluation of packaging (including multichip) schemes.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Acceleration Factors for IC Leakage Current in a Steam Environment

Leakage current measurements were made across the surface of silicon test chips up to a temperature of 130°C (403°K) and 70% relative humidity (RH) to develop a more accelerated temperature-humidity-bias corrosion test. Several equations were fitted to the data in order to extrapolate the surface conductivity data to operating conditions. A smooth transistion from atmospheric pressure into the pressurized steam region was observed. The leakage current acceleration factor is the same at 130°C/60%RH and 85°C/85%RH for bare gold electrodes. For nitride-covered aluminum conductors the equlvalent conditions are 130°C/65%RH or 85°C/85%RH. The advantage in the steam region is a larger temperature differential between the sample and saturation; approximately 15°C as opposed to 4°C for the 85°C/85%RH. This makes the steam test easier to control, but might raise the temperature beyond the decomposition limits for organic packaging materials. For inorganic systems with nitride-covered aluminum electrodes, an acceleration by a factor of three compared to 85°%C/85%RH can be obtained at 140°C/70%RH or 17°C/60%RH. Coefficients were determined by multiple regression analysis for three forms of equations which express the surface conductivity in terms of reciprocal absolute temperature and RH. The acceleration factors determined by a power law are consistently lower than those determined by two forms of an exponential equation.