Silicon-silicon Dioxide Interface Research Articles

A gate leakage current-powered loadless 4T SRAM with immunity against random dopant fluctuation and surface roughness in silicon-silicon dioxide interface

The sensitivities of the data hold, read and write performances for the gate leakage-powered loadless 4T SRAM cell on the variations in the MOSFETs’ gate leakage currents are examined by SPICE Monte Carlo simulations in 32 nm technology. The standard deviations in the gate leakage current variations are taken from the device simulation results in which the variations are caused by the random dopant fluctuation and the surface roughness in silicon-silicon dioxide interface. It is shown that the static noise margin (SNM) in the data hold state is 60 mV at 1 V power supply voltage for the −5σ cell with the MOSFETs’ threshold voltage variations taken into consideration. The read SNM and the write SNM are shown to be 160 mV and 440 mV for the −5σ cell, respectively, which are better than the 6TSRAM cell.

Unravelling the silicon-silicon dioxide interface under different operating conditions

Silicon dioxide (SiO2) has played a critical role in the development of high-efficiency silicon (Si)-based photovoltaic devices. Recently, it has experienced a renaissance as an interlayer in many of the new contact passivating structures. Studies have extensively investigated the recombination process at the Si–SiO2 interface, however, only little is known about the impact of temperature on the surface recombination. In this study, we investigate the recombination at the Si–SiO2 interface by varying the temperature, excess carrier density, and dielectric fixed charge. An improved lifetime is observed with increasing temperature. A forming gas anneal is used to improve the passivation quality, however, at higher temperatures, the hydrogenated interface passivation degrades due to increased surface state density. The degradation is stronger for corona-charged SiO2, due to the instability of the corona charge within the dielectric. Using the extended Shockley-Read Hall recombination model, the Si–SiO2 interface defects’ parameters are extracted. Most importantly, we determine the value and the temperature-dependence of the capture cross-sections at this interface.

CHARACTERIZATION OF THE ELECTROPHYSICAL PROPERTIES OF SILICON-SILICON DIOXIDE INTERFACE USING PROBE ELECTROMETRY METHODS

Introduction of submicron design standards into microelectronic industry and a decrease of the gate dielectric thickness raise the importance of the analysis of microinhomogeneities in the silicon-silicon dioxide system. However, there is very little to no information on practical implementation of probe electrometry methods, and particularly scanning Kelvin probe method, in the interoperational control of real semiconductor manufacturing process. The purpose of the study was the development of methods for nondestructive testing of semiconductor wafers based on the determination of electrophysical properties of the silicon-silicon dioxide interface and their spatial distribution over wafer’s surface using non-contact probe electrometry methods.Traditional C-V curve analysis and scanning Kelvin probe method were used to characterize silicon- silicon dioxide interface. The samples under testing were silicon wafers of KEF 4.5 and KDB 12 type (orientation <100>, diameter 100 mm).Probe electrometry results revealed uniform spatial distribution of wafer’s surface potential after its preliminary rapid thermal treatment. Silicon-silicon dioxide electric potential values were also higher after treatment than before it. This potential growth correlates with the drop in interface charge density. At the same time local changes in surface potential indicate changes in surface layer structure.Probe electrometry results qualitatively reflect changes of interface charge density in silicon-silicon dioxide structure during its technological treatment. Inhomogeneities of surface potential distribution reflect inhomogeneity of damaged layer thickness and can be used as a means for localization of interface treatment defects.

60Co γ-ray induced gain degradation in bipolar junction transistors

Commercial indigenously made npn and pnp bipolar junction switching transistors used for space applications are investigated for 60Co γ-ray induced effects. The on-line as well as off-line measurements indicate that the forward current gain of the transistors decreases significantly as the accumulated dose increases. Excess base current model is employed to account for the current gain degradation. The pnp transistor undergoes as much degradation as the npn type. It is found that bulk degradation by displacement damage is the dominant mechanism leading to reduction in forward current gain of npn transistors. On the other hand it appears that, in addition to bulk damage, surface degradation due to accumulation of interface states at the silicon-silicon dioxide interface also contributes significantly to gain degradation in pnp transistor as evident from thermal annealing studies. Further, estimation reveals that the transistor with larger base width has higher displacement damage factor.

Compact modeling and simulation of nanoscale fully depleted DG-SOI MOSFETS

A two dimensional analytical model for nanoscale fully depleted double gate SOI MOSFET is presented. Green's function solution technique is adopted to solve the two dimensional Poisson's equation using Dirichlet's and Neumann's boundary conditions at silicon-silicon di-oxide interface. Based on the derived 2D potential distribution, surface potential distributions in the Si film are analytically obtained. The calculated minimum surface potential is used to develop an analytic threshold voltage model. Simulation is done using ATLAS simulator for a 65 nm device and the results obtained are compared with the proposed 2D model. The model results are found to be in good agreement with the simulated data and other published results.

The 1/f Noise Performance for TFTs Fabricated in Three TFT Technologies: Monocrystalline Silicon on Glass, Low Temperature Polysilicon on Glass, and Silicon on Insulator

The 1/f noise characteristics were measured for CMOS devices fabricated in three different process technologies: conventional SOI (SmartCut), monocrystalline silicon on glass (SiOG) and low temperature polysilicon (LTPS). Noise slope and bias current parameters, from the SPICE2 low frequency noise model, were extracted from the 1/f measurements. The SPICE2 noise coefficient parameter, Kf, was extracted for each device. SOI PMOS (which exhibit the least amount of 1/f noise) establish a baseline noise level to compare TFT technologies against. SiOG and LTPS PMOS devices exhibit noise coefficients that were 1.89 and 2.93 times larger than the SOI PMOS device, respectively. The degraded 1/f performance of SiOG and LTPS devices when compared to SOI can be linked to the silicon-silicon dioxide interface trap density. All devices exhibited similar 1/f noise slopes, between 0.8 and 0.98, where processing variations were found to correspond to low slope values.

JES Classics: ECS Science at Its Best: Looking Back, Charging Ahead

The silicon-silicon dioxide (Si-SiO2) interface system is the heart and soul of silicon microelectronic devices and integrated circuits. The importance of this interface system for device fabrication and operation began with the recognition that a thermally-grown SiO2 layer on silicon can serve as both a diffusion barrier to dopants and a means to reduce the silicon surface state density.

Sub-threshold analysis and drain current modeling of polysilicon thin-film transistor using Green's function approach

An analytical analysis for a poly-crystalline silicon thin-film transistor is presented. The Green's function approach is adopted to solve the two-dimensional Poisson's equation using Neumann's boundary conditions at the silicon-silicon di-oxide interface. The developed model gives an insight of device behavior due to the effect of traps and also grain-boundary effect. The analysis of threshold voltage depicts short-channel effects and drain-induced barrier lowering. The model is extended to analyze the transfer characteristics and obtain the transconductance of the device. The results obtained show good agreement with the numerical model and with simulated results, thus proving the validity of our model.

The Effect of γ Radiation on the Temperature Dependence of the Surface Generation Velocity at a Si–SiO[sub 2] Interface

We have studied the effect of γ radiation on the generation characteristics of a silicon-silicon dioxide (Si-SiO2) interface formed upon thermal oxidation of the surface of silicon. The irradiation leads to the appearance of a temperature dependence of the surface generation velocity. This effect is related to the formation of radiation-induced traps capable of exchanging trapped carriers with the bulk of a semiconductor by means of tunneling emission.

Silicon radiation detectors

The rapid progress of the past 20 years in silicon radiation detectors is reviewed. The availability of silicon as an almost ideal semiconductor material is one of the main reasons for this progress. The well-defined properties of the silicon-silicon dioxide interface allowed the development of detector structures beyond the structure of a classical diode detector, which was practically the only silicon detector structure 20 years ago. All new structures make use of an electric field parallel to the large surface of the detector. Improvements in the production of silicon detectors has lead to a substantial decrease of the detector leakage current. These detectors can achieve their best performance very close to or at room temperature.

The effect of ultrasonic treatment on the generation characteristics of a Si-SiO2 interface

We have studied the effect of ultrasonic treatment on the generation characteristics of a silicon-silicon dioxide (Si-SiO2) interface obtained by thermal oxidation of the surface of silicon. The ultrasonic treatment leads to a decrease in the surface generation rate and an increase in the generation lifetime of minority charge carriers. These effects are related to a transformation of the defect structure of a transition layer at the Si-SiO2 interface and in the adjacent region of silicon.

Hot-Carrier Lifetime Dependence on Channel Width and Silicon Recess Depth in N-Channel Metal-Oxide-Semiconductor Field-Effect-Transistors with the Recessed Local Oxidation of Silicon Isolation Structure

Narrow width n-channel metal-oxide-semiconductor field-effect-transistors (nMOSFETs) fabricated with recessed local oxidation of silicon (R-LOCOS) isolation structures and deeper field oxide recess exhibit less hot-carrier degradation as compared to wide channel devices when stressed under the maximum substrate current condition. Through the investigation of many possible causes, such as channel stop doping effect, lateral channel electric field, mechanical stress effect, and recess depth effect, the cause of the smaller degradation in narrow channel nMOSFETs was found. This was due to a hole-attractive vertical electric field across the width of the narrow channel nMOSFET, which results in less interaction of the channel hot electrons with the silicon-silicon dioxide interface, and thus contributing to less interface-state generation. It was also found that a deeper field oxide recess in narrow channel nMOSFETs leads to lesser hot-carrier degradation, which is possibly related to the reduced impact ionization rate in the channel.

Oxidation of semiconductors and the constitution of interfaces

The effects of the self-organization of phase boundaries in semiconductors (separation surfaces and reaction zones) are considered for semiconductor oxidation, the most technologically important process in microelectronics. The analysis of kinetic data yields entropies of activation of these processes and demonstrates that the silicon-oxygen system shows the strongest self-organization of the reaction zone—the silicon-silicon dioxide interface.

Impact of Scaling on CMOS Chip Failure Rate, and Design Rules for Hot Carrier Reliability

Silicon-hydrogen bonds passivate the interface defects at the silicon-silicon dioxide interface of CMOS transistors. The activation of these bonds and subsequent creation of interface traps is an important source of transistor degradation at current operating conditions. There is now evidence for a distribution in the activation energies of these bonds instead of a single threshold value. We show that conventional CMOS scaling rules are substantially affected by this energy distribution, as it causes an increased probability of smaller devices having lower activation thresholds and therefore faster activation times. Further, we quantify the voltage shift necessary to overcome the decreased yield due to the increased number of early device failures, and show, for 0.1 μm MOSFET scaling, that this shift can be a considerable fraction of the conventionally designed supply voltage.

Simulation of Clustering and Pile-Up during Post-Implantation Annealing of Phosphorus in Silicon

We report on the simulation of the annealing behavior of medium dose (1013–1014 cm-2) implanted phosphorus in silicon. It is shown that the transient clustering of phosphorus has to be taken into account in order to achieve consistent simulation results. The pile-up of phosphorus at the silicon-silicondioxide interface is considered by including a diffusion-segregation term in the diffusion-reaction equations. We show how the phosphorus clustering impacts the phosphorus amount in the pile-up layer and compare the simulation results with available experimental data.

Si-PIN X-ray detector technology

PIN diodes and other test structures have been fabricated on both n- and p-type, high-resistivity, Floating-Zone (FZ) silicon substrates. Different alternative extrinsic-gettering techniques have been adopted to the purpose of meeting the required specification of a detector leakage current density lower than 1 nA/cm 2. Phosphorus-doped polysilicon gettering provided the best results on n-type Si with a leakage current density lower than 0.2 nA/cm 2 at 100 μm depletion width. On the contrary, devices made on p-type substrates exhibited a leakage current density two orders of magnitude higher. A proper control of the oxide charge at the silicon-silicon dioxide interface was found to be crucial in obtaining a predictable behavior of PIN diode detectors. Some degradation of the reverse leakage current has been observed after device dicing and bonding.

Effects of oxide interface traps and transient enhanced diffusion on the process modeling of PMOS devices

We present a model which simulates the trapping of arsenic and boron dopants at the silicon-silicon dioxide interface, and demonstrate that this model gives significantly more accurate doping profiles for a wide range of PMOS devices, as characterized by the device Threshold Voltage. In addition, a newly-developed Transient Enhanced Diffusion (TED) model is applied for the first time to the process simulation of buried-channel PMOS devices, predicting an enhanced Short Channel Effect and Drain Induced Barrier Lowering (DIBL) effect. By using both these models, an excellent agreement is achieved between simulated and measured device characteristics for PMOS devices with gate lengths varying from 2 to 0.4 /spl mu/m, over a wide range of bias conditions and operating temperatures.

Interface states induced by the presence of trapped holes near the silicon–silicon-dioxide interface

Trapped holes are shown to induce ‘‘slow’’ interface states by their presence that are distinctly different from other types of interface states. These slow states can be alternately introduced and removed by sequential hole generation and annihilation. Various experiments and techniques are used to rule out explanations involving artifacts due to lateral nonuniformities in the hole trapping.

Gate Quality Oxides Prepared by Rapid Thermal Chemical Vapor Deposition

AbstractAs the feature size of MOSFET devices shrink, issues such as thermal budget associated with controlling channel doping profiles and oxide growth kinetics raise concerns about using thermally grown furnace oxides for deep-submicron device applications. To address these concerns, we have developed a new RTCVD oxide process using a gas system of silane and nitrous oxide. The RTCVD oxides are deposited in a lamp-heated, cold wall, RTP system. Deposition rates ranging from 55 Å/min. to 624 Å/min. can be achieved at 800°C with silane nitrous oxide flow rate ratio of 2% and total pressure ranging from 3 to 10 Torr. The results indicate that this RTCVD process can be used to deposit both thin gate and thick isolation insulators for single wafer processing. Deposition rates of the RTCVD oxides exhibit a nonlinear dependence on the total deposition pressure. Electrical characterization of the as-deposited RTCVD oxides shows a mid-gap interface trap density of < 5×1010 eV−1 cm−2 and an average breakdown field of 13MV/cm. AES, RBS and TEM analyses have been used to study surface cleaning effects on the silicon-silicon dioxide interface quality and to determine the chemical composition of the RTCVD oxides. The results show that RTCVD oxides with stoichiometric composition and atomic flat silicon-silicon dioxide interface can be achieved using silane nitrous oxide flow rate ratio of <2%. I-V characteristics and transconductance degradation under hot carrier stress for MOSFET's using as-deposited RTCVD gate oxides have been found to be comparable to those of MOSFET's using thermal gate oxides.

Thermally activated capture of charge carriers into irradiation induced Si/SiO2 interface states

Deep-level transient spectroscopy (DLTS) measurements of capture cross sections of Co60 induced silicon-silicon dioxide (Si/SiO2) interface states have been performed. For the accurate analysis of measured data a new technique based on numerical solutions of the emission rate equations has been used. Computer simulations of DLTS measurements have been compared with measured data in order to extract reliable results in the case of nonexponential transients. We show that the capture cross sections are thermally activated. Together with earlier consistent results on the same kind of centers, this leads us to the conclusion that vibronic properties play important roles for the electron capture into these traps.