Silicon Sensor Technologies Research Articles

ATLAS pixel IBL modules construction experience and developments for future upgrade

The first upgrade of the ATLAS Pixel Detector is the Insertable B-Layer (IBL), installed in May 2014 in the core of ATLAS. Two different silicon sensor technologies, planar n-in-n and 3D, are used. Sensors are connected with the new generation 130nm IBM CMOS FE-I4 read-out chip via solder bump-bonds. Production quality control tests were set up to verify and rate the performance of the modules before integration into staves. An overview of module design and construction, the quality control results and production yield will be discussed, as well as future developments foreseen for future detector upgrades.

The Insertable B-Layer of the Atlas experiment for the Run-2 at the Large Hadron Collider

The Pixel Detector of the ATLAS experiment has shown excellent performance during the whole Run-1 of Lhc. Taking advantage of the long shutdown, the detector was extracted from the experiment and brought to surface, to equip it with new Service Quarter Panels, to repair modules and to ease installation of the Insertable B-Layer (Ibl). Iblis a fourth layer of pixel detectors and has been installed in May 2014 between the existing Pixel Detector and a new smaller radius beam pipe at a radial distance of 3.3cm from the beam axis. The realization of the Iblrequired the development of several new technologies and solutions in order to overcome the challenges introduced by the extreme environment and working conditions, such as the high radiation levels, the high pixel occupancy and the need of an exceptionally low material budget. Two silicon sensor technologies have been adopted for the Iblmodules: planar and 3D. Both of these are connected via bump-bonding to the new Fe-i4front-end read-out chip. Furthermore, the physics performance will be improved through the reduction of pixel size while, targeting for a low material budget, a new mechanical support using lightweight staves and a CO2 based cooling system have been adopted. An overview of the Iblproject as well as the experience in its construction is presented, focusing on adopted technologies, modules and staves production, qualification of assembly procedure, integration of staves around the beam pipe and commissioning of the detector.

The Pixel Detector of the ATLAS experiment for the Run2 at the Large Hadron Collider

The Pixel Detector of the ATLAS experiment has shown excellent performance during the whole Run-1 of LHC. Taking advantage of the long shutdown, the detector was extracted from the experiment and brought to surface, to equip it with new service quarter panels, to repair the modules and to ease installation of the Insertable B-Layer (IBL). The IBL is a fourth layer of pixel detectors, and has been installed in May 2014 between the existing Pixel Detector and a new smaller radius beam-pipe at a radius of 3.3 cm. To cope with the high radiation and pixel occupancy due to the proximity to the interaction point, a new read-out chip and two different silicon sensor technologies (planar and 3D) have been developed. Furthermore, the physics performance will be improved through the reduction of pixel size while, targeting for a low material budget, a new mechanical support using light weight staves and CO2 based cooling system have been adopted. An overview of the refurbishing of the Pixel Detector and the IBL project as well as the experience in its construction will be presented, focusing on adopted technologies, module and stave production, qualification of assembly procedure, integration of staves around the beam pipe and commissioning of the detector.

The Pixel Detector of the ATLAS experiment for Run 2 of the Large Hadron Collider

The Pixel Detector of the ATLAS experiment has shown excellent performance during the whole Run 1 of the LHC. Taking advantage of the long shutdown, the detector was extracted from the experiment and brought to surface in order to equip it with new service quarter panels, to repair modules, and to ease installation of the Insertable B-Layer (IBL). The IBL is the fourth layer of the Run 2 Pixel Detector, and it was installed at a radius of 3.3 cm in May 2014 between the existing Pixel Detector and the new smaller-radius beam pipe. To cope with the high radiation and pixel occupancy due to the proximity to the interaction point, a new read-out chip and two different silicon sensor technologies (planar and 3D) have been developed. Furthermore, the physics performance is expected to improve through the reduction of pixel size. As well, targeting for a low material budget, a new mechanical support using lightweight staves and a CO2 based cooling system were adopted. An overview of the IBL project as well as the experience in its construction is presented, focusing on adopted technologies, module and staves production, qualification of assembly procedure, integration of staves around the beam pipe, and commissioning of the detector.

Comparison of Planar and 3D Silicon Pixel Sensors Used for Detection of Low Energy Antiprotons

The principal aim of the AEgIS experiment at CERN is to measure the acceleration of antihydrogen due to Earth's gravitational field. This would be a test of the Weak Equivalence Principle, which states that all bodies fall with the same acceleration independently of their mass and composition. The effect of Earth's gravitational field on antimatter will be determined by measuring the deflection of the path of the antihydrogen from a straight line. The position of the antihydrogen will be found by detecting its annihilation on the surface of a silicon detector. The gravitational measurement in AEgIS will be performed with a gravity module, which includes the silicon detector, an emulsion detector and a scintillating fibre time-of-flight detector. As the experiment attempts to determine the gravitational acceleration with a precision of 1%, a position resolution better than 10 μm is required. Here we present the results of a study of antiproton annihilations in a 3D silicon pixel sensor and compare the results with a previous study using a monolithic active pixel sensor. This work is part of a larger study on different silicon sensor technologies needed for the development of a silicon position detector for the AEgIS experiment. The 3D detector together with its readout electronics have been originally designed for the ATLAS detector at the LHC. The direct annihilation of low energy antiprotons ( ~ 100 keV) takes place in the first few μm of the silicon sensor and we show that the charged products of the annihilation can be detected with the same sensor. The present study also aims to understand the signature of an antiproton annihilation event in segmented silicon detectors and compares it with a GEANT4 simulation model. These results will be used to determine the geometrical and process parameters to be adopted by the silicon annihilation detector to be installed in AEgIS.

The ATLAS Insertable B-Layer project

The ATLAS experiment will upgrade its pixel detector with the installation of a new pixel layer in 2013–14. The new sub-detector, named Insertable B-layer (IBL), will be installed between the existing pixel detector and a new smaller radius beam-pipe at a radius of 3.3 cm. To cope with the high radiation and pixel occupancy due to the proximity to the interaction point, a new read-out chip and two different silicon sensor technologies (planar and 3D) have been developed. Furthermore, the physics performance should be improved through the reduction of pixel size while a low material budget should be imposed. A new mechanical support using lightweight staves and a CO2 based cooling system is used. An overview of the IBL project and the status of the production of staves and the qualification of the assembly procedure, the loaded module electrical integrity and the read-out chain will be presented.

Overview of the ATLAS Insertable B-Layer (IBL) Project

The upgrades for the ATLAS Pixel Detector will be staged in preparation for high luminosity LHC. The first upgrade for the Pixel Detector is the construction of a new pixel layer which will be installed during the first shutdown of the LHC machine, in 2013–2014. The new detector, called the Insertable B-Layer (IBL), will be installed between the existing Pixel Detector and a new, smaller radius beam-pipe at a radius of 3.3cm. The IBL has required the development of several new technologies to cope with increased radiation and pixel occupancy and also to improve the physics performance through reduction of the pixel size and a more stringent material budget. The IBL presents several changes to the design of the present ATLAS Pixel Detector: two different and promising silicon sensor technologies, planar n-in-n and 3D, will be used for the IBL. A new read-out chip FE-I4 has been designed in 130nm technology, the material budget is minimized by using new lightweight mechanical support materials and a CO2 based cooling system has been developed. An overview of the IBL project, of the module design and the qualification for these sensor technologies with particular emphasis on irradiation and beam tests will be presented.

The ATLAS Insertable B-Layer (IBL) project

Preparing for the high luminosity LHC phase, the ATLAS experiment will upgrade its Pixel Detector with the installation of a new pixel layer. The new sub detector, called the Insertable B-Layer (IBL), will be installed during the LHC first shut down in 2013–2014, in between the innermost current pixel layer and the beampipe.To cope with the high radiation and pixel occupancy due to the proximity to the interaction point, a new readout chip FE-I4 and two different silicon sensor technologies, planar and 3D have been developed. Furthermore, the physics performance should be improved through the reduction of pixel size and a new mechanical support using lightweight staves.Two pre-series staves were made in order to qualify the assembly procedure, the loaded module electrical integrity and the readout chain before going into production.

Overview of the ATLAS insertable B-layer project

The upgrades for the ATLAS Pixel Detector will be staged in preparation for high luminosity LHC. The first upgrade for the PixelDetector will be the construction of a new pixel layer which will beinstalled during the first shutdown of the LHC machine, foreseen in2013-14. The new detector, called the Insertable B-layer (IBL), willbe installed between the existing Pixel Detector and a new smallerradius beam-pipe. The IBL will be located at an average radius of3.3 cm. The IBL required specific developments to cope withincreased radiation and pixel occupancy and also to improve thephysics performance through reduction of the pixel size and a morestringent material budget. Two silicon sensor technologies have beenpushed forward to fulfill the IBL requirements: thin planar sensorsand 3D double side sensors, both with slim edge. An overview of theIBL project, of the module design and qualification with particularemphasis on irradiation tests will be presented.

Irradiation and beam tests qualification for ATLAS IBL Pixel Modules

The upgrade for the ATLAS detector will have different steps towards HL-LHC. The first upgrade for the Pixel Detector will consist in the construction of a new pixel layer which will be installed during the first shutdown of the LHC machine (foreseen for 2013–2014). The new detector, called Insertable B-Layer (IBL), will be inserted between the existing Pixel Detector and a new (smaller radius) beam-pipe at a radius of 33mm. The IBL will require the development of several new technologies to cope with the increase in the radiation damage and the pixel occupancy and also to improve the physics performance, which will be achieved by reduction of the pixel size and of the material budget. Two different promising silicon sensor technologies (Planar n-in-n and 3D) are currently under investigation for the Pixel Detector. An overview of the sensor technologies' qualification with particular emphasis on irradiation and beam tests is presented.

Overview of the ATLAS insertable B-layer (IBL) project

The upgrades for the ATLAS Pixel Detector will be staged in preparation for high luminosity LHC. The first upgrade will be the construction of a new pixel layer which will be installed during the first shutdown of the LHC machine, foreseen in 2013–2014. The new detector, called the Insertable B-layer (IBL), will be installed between the existing Pixel Detector and a new, smaller radius beam-pipe at a radius of 3.3cm. The IBL will require the development of several new technologies to cope with increased radiation and pixel occupancy and also to improve the physics performance through reduction of the pixel size and a more stringent material budget. Two silicon sensor technologies, planar and 3D, are currently under investigation for the IBL. An overview of the IBL project, of the module design and the qualification for these sensor technologies is presented.

ATLAS IBL sensor qualification

The upgrade of the ATLAS detector will undergo different phases towards high luminosity LHC. The first upgrade for the Pixel Detector will consist in the construction of a new pixel layer which will be installed during the first shutdown of the LHC machine (foreseen for 2013–14). The new detector, called Insertable B-Layer (IBL), will be inserted between the existing Pixel Detector and a new (smaller radius) beam-pipe at a radius of 3.2 cm. The IBL will require the development of several new technologies to cope with increase of radiation or pixel occupancy and also to improve the physics performance which will be achieved by reduction of the pixel size and of the material budget. Two different promising Silicon sensor technologies (Planar n-in-n and 3D) are currently under investigation for the Pixel Detector.An overview of the sensor technologies qualification with particularemphasis on irradiation and beam tests will be presented.

Silicon sensor developments for the CMS Tracker upgrade

Preparing for the high-luminosity phase of LHC the CMS Tracker collaboration has started a campaign to identify the future planar silicon sensor technology baseline for a new Tracker. A variety of 6 inch wafers have been ordered in different thicknesses and technologies at HPK. Thicknesses ranging from 50μm to 300μm are explored on float-zone, magnetic Czochralski and epitaxial material both in n-in-p and p-in-n versions. p-stop and p-spray are explored as isolation technologies for the n-in-p type sensors as well as the feasibility of double metal routing on 6 inch wafers. To explore the limits of the technologies many different structures have been designed to answer different questions, e.g. geometry, Lorentz angle, radiation tolerance, annealing behavior, read-out schemes.This contribution provides an overview of the individual structures and their characteristics and summarizes measurements done on small strip sensors before and after irradiations.

Characterization of new hybrid pixel module concepts for the ATLAS Insertable B-Layer upgrade

The ATLAS Insertable B-Layer (IBL) collaboration plans to insert a fourth pixel layer inside the present Pixel Detector to recover from eventual failures in the current pixel system, especially the b-layer. Additionally the IBL will ensure excellent tracking, vertexing and b-tagging performance during the LHC phase I and add robustness in tracking with high luminosity pile-up. The expected peak luminosity for IBL is 2 to 3·1034 cm−2s−1 and IBL is designed for an integrated luminosity of 700 fb−1. This corresponds to an expected fluence of 5·1015 1 MeV neqcm−2 and a total ionizing dose of 250 MRad.In order to cope with these requirements, two new module concepts are under investigation, both based on a new front end IC, called FE-I4. This IC was designed as readout chip for future ATLAS Pixel Detectors and its first application will be the IBL. The planar pixel sensor (PPS) based module concept benefits from its well understood design, which is kept as similar as possible to the design of the current ATLAS Pixel Detector sensor. The second approach of the new three dimensional (3D) silicon sensor technology benefits from the shorter charge carrier drift distance to the electrodes, which completely penetrate the sensor bulk. Prototype modules of both sensor concepts have been build and tested in laboratory and test beam environment before and after irradiation. Both concepts show very high performance even after irradiation to 5·1015 1 MeV neqcm−2 and meet the IBL specifications in terms of hit efficiency being larger than 97%. Lowest operational threshold studies have been effected and prove independent of the used sensor concept the excellent performance of FE-I4 based module concepts in terms of noise hit occupancy at low thresholds.

Silicon Sensor Technologies for the ATLAS IBL Upgrade

An overview of radiation hard planar and 3D pixel sensor technologies currently under development for ATLAS upgrades is presented. T * he first upgrade will be the installation in 2013 of an additional pixel layer inside the current Detector, the Insertable B Layer (IBL). The two technologies are competing to equip the IBL. The IBL sensor qualification procedure is described. Beam test results of un-irradiated and irradiated planar and 3D sensors are presented.

Silicon sensor development for the CMS tracker upgrade

CMS started a campaign to identify the future silicon sensor technology baseline of the new tracker for the high-luminosity phase of LHC. We ordered a large variety of 6 inch wafers in different thicknesses and technologies at producer Hamamatsu. Thicknesses ranging from 50 microns to 300 microns are explored on Floatzone, Magnetic Czochralski and Epitaxial Silicon both in n-in-p and p-in-n versions. P-stop and p-spray are explored as isolation technologies for the n-in-p type sensors as well as the feasibility of double metal routing on 6 inch wafers. Each wafer contains many different structures to answer different questions, e.g. geometry, Lorentz angle, radiation tolerance, annealing behavior or read-out schemes. Dedicated process test-structures, as well as diodes, mini-sensors, long and very short strip sensors and real pixel sensors have been designed for this evaluation. This contribution provides an overview of the campaign and summarizes interesting measurements performed so far.

System architecture of Detector Control and safety for the ATLAS Inner Detector Upgrade

In the current ATLAS Upgrade plan a new Inner Detector (ID) based upon silicon sensor technology is being considered. The operational monitoring and control of the ID will be very demanding. The Detector Control System (DCS) is a common tool that is essential for the operational safety of a system. Even at this early stage the DCS system architecture has to be defined such that it is well integrated and optimized for its later implementation and use. For example the DCS diagnostics for the front-end (FE) chips is a serious option being considered that needs an early requirement and specification definition. In addition one of the main constraints is the service reuse between the service patch panels of the ATLAS ID and the counting room that limits the number of electrical lines to be reused. Conceptual differences in terms of readout architecture and layout have been identified between the strip and the pixel detector that lead to two distinct architectures. Nevertheless, the limitation of available electrical lines going to the counting room as well as the low material budget requirements inside the ID volume are two major constraints that lead the ID to consider an on-detector radiation hard integrated circuitry for the slow control. At this stage of the project, the definitions of the logical actions and protocol for the ADCs of such a chip are still being specified. In addition the experience gained from the current ID will be essential for the guidance of tuning the future DCS architecture in the coming years.

Polar Heterostructure for Multifunction Devices: Theoretical Studies

We examine the potential of devices based on heterostructures made from highly polar materials and semiconductors. Our calculations show that such functional devices have superior sensor properties and transistor properties. The basis device examined is based on the use of a thin oxide with high piezoelectric coefficients or pyroelectric coefficients under the gate region. Channel charge and current are controlled by gate voltage, temperature, or stress. We examine the performance of three classes of heterostructures that form the basis of important semiconductor technologies: 1) Si-SiO/sub 2/-BaTiO/sub 3/ heterostructure junctions that would be an important breakthrough for silicon sensor technology; 2) GaN-AlN-BaTiO/sub 3/ heterostructure junctions that would be important especially in high temperature sensor application; and 3) GaAs-AlGaAs-BaTiO/sub 3/ heterostructure field effect transistors. The calculations show that with a very thin polar material layer we can have a highly sensitive sensor and transistor. For optimum performance, the polar material (piezoelectric or pyroelectric) layer thickness should be /spl sim/30 /spl Aring/.

Metal piezoelectric semiconductor field effect transistors for piezoelectric strain sensors

In this letter, we examine the potential of a functional device that can have good transistor and stress sensor properties. The device examined is based on the use of a thin oxide with high piezoelectric coefficients under the gate region. Channel charge and current are controlled by gate voltage or by stress. We examine the performance of two classes of heterostructures that are important semiconductor technologies: (i) Si∕SiO2∕BaTiO3 heterostructure junctions that would be an important breakthrough for silicon sensor technology and (ii) GaN∕AlN∕BaTiO3 heterostructure field effect transistors. The calculations show that with a very thin piezoelectric layer we can have a highly sensitive stress sensor and transistor. For optimum performance, the piezoelectric layer thickness should be ∼30–60Å.

Powering sensor networks

This paper describes the sensor networks that are wireless systems in which large number of sensors can be deployed. A snapshot of the first-generation hardware and software for sensor networks, the requirements of the sensor nodes by their capabilities, and an outlook on future implementations are focused. These networks have been enabled in part by advancements in silicon sensor technology, low-power microcontrollers, chip-based radios, ad-hoc networking protocols, and operating systems and languages for embedded systems.