Silicon Recess Research Articles

Silicon nitride spacer etching selectively to silicon using CH3F/O2/He/SiCl4 plasma

Using CH3F/O2/He based chemistries in high density plasmas for silicon nitride spacer etching, loss of silicon in active source/drain regions of CMOS transistors can be observed. Minimizing the so-called silicon recess during nitride spacer etching is extremely difficult to achieve but mandatory since it directly impacts the device performance. In this work, the authors investigated the benefits of CH3F/O2/He/SiCl4 plasma to limit this recess. Using x-ray photoelectron spectroscopy, the mechanism for high Si3N4/Si selectivity is identified as the formation of a preferential thick SiOxFyClz passivation layer, generated at the silicon surface. The silicon damage is reduced by the growth of this thick layer, limiting the transfer of the reactive layer into the silicon film. These results have been confirmed on pattern structures for fully depleted silicon on insulator 14 nm technology showing the benefit of CH3F/O2/He/SiCl4 etch plasma compared to CH3F/O2/He plasma.

Strained p-Channel MOSFET Fabrication Challenge and Perspective for the 28-Nm Technology Node and Beyond

Carrier mobility enhancement technique was introduced to ULSI manufacture since 90-nm technology node. As one of promising mobility enhancement techniques, the strain/stress at the channel region of metal-oxide-semiconductor field effect transistors (MOSFETs) modulates the lattice constant and band structure of silicon then enhances the hole/electron mobility. [1] The high mobility gives high source injection velocity into the quasi-ballistic transport channel which can provide high drive current and high circuit speed of MOSFETs. [2] Among a great variety of mobility enhancement techniques by applying stress to induce appropriate strain in the p-channel region, forming embedded epitaxial Si1-xGex with recessed Source/Drain (S/D) structure has been reported as one powerful technique. [3] The Sigma-shaped silicon recess profile is applied before epitaxial Si1-xGexgrowth, because the strain force on the channel of MOSFET is increased effectively by narrowing spacing between source and drain. [4] In this manuscript, we utilized one-step and two-step dry etch process with the same alkaline solution wet etch to form Sigma-shaped silicon recess profile for the planar p-channel MOSFETs. After comparing the recess depth loading correlated to the pitch of gate electrodes (Table 1), we also studied the tunable capability and limitations on tip depth, tip proximity and total depth of Sigma-shaped trench for these two different dry etch processes. The strict profile control of Sigma-shaped profile is not only led by the device performance variation demand but also needed to get the excellent epitaxial Si1-xGex crystallinity. Besides that, Si-C bond on the trench surface could inhibit the epitaxial Si1-xGex growth, thus resulting in defects on S/D area. We proved that high H2 volume ash process could effectively remove the Si-C bond at trench surface and greatly reduce the Si1-xGexdefect counts. (Fig. 1) Recently, the further down-scaling of planar MOSFETs technology is facing a serious physical limitation which results in short-channel effects (SCEs). Multiple-gate FETs or Fin structure FETs are already adopted in the fabrication process for the excellent control of SCEs from 20-nm technology node. Unlike the conventional planar transistor, a significant portion of the drain current is conducted along the fin sidewalls in FinFETs. Therefore, to realize a large mobility enhancement, the strain/stress techniques of FinFETs should be significantly different from embedded Si1-xGex techniques of traditional planar devices. The Pi-shaped Si1-xGex (Π-Si1-xGex) should be induced to encapsulate the silicon on the top and sidewalls of the narrow fins. [5] In this work, the Π-Si1-xGex stressors should be grown on the top and sidewalls of fins in the S/D regions of p-channel FinFETs. However, due to the loading effect of traditional silicon nitride (SIN) spacer etch, the epitaxial Si1-xGex growth could be hindered by the existence of SIN spacer stringer at the sides of the fin in some special pattern density area. To solve this issue, multi-cycle SIN etch process was attempted in the spacer open step. Compared with the conventional etch process, the multi-cycle SIN etch process delivers the excellent control of spacer pull back loading at universal pattern density area. (Fig. 2) In order to protect the SIN capping layer on the gate top corner and clearly remove the SIN spacer at the top area of fins, the gas types, gas ratio and other parameters are carefully optimized in SIN spacer etch process. We successfully decoupled the trade-off line of capping layer protection and the SIN spacer pull back. Additionally, by balancing the isotropic and anisotropic recess parts in the whole process, we demonstrated the recessed fin structure with flat and smooth surface on the top area, which would be benefit for future good crystalline and well controlled Π-Si1-xGexgrowth. (Fig. 3) ACKNOWLEDGMENT This work was partially sponsored by Program of Shanghai Technology Chief Scientist (B type).

Patterning of silicon nitride for CMOS gate spacer technology. III. Investigation of synchronously pulsed CH3F/O2/He plasmas

Si3N4 spacer etching processes are one of the most critical steps of transistor fabrication technologies since they must be at the same time very anisotropic to generate straight spacer profiles and extremely selective to silicon in order to minimize the silicon consumption in source/drain regions. Minimizing the silicon recess and ion-induced damages to silicon surfaces are key criterions for fully depleted silicon on insulator technologies in order to ensure a high surface quality for the subsequent step of silicon epitaxy. In this work, the authors investigate synchronously pulsed CH3F/O2/He plasmas for the etching of Si3N4 spacers selectively toward Si (the selectivity typically relies on the oxidation of the silicon layer). First, they compare the Si3N4 and silicon etch rates measured in continuous wave (CW) plasmas, while varying the [CH3F]/[O2] ratio, to the etch rates measured using pulsed plasmas. Using angle resolved x-ray photoelectron spectroscopy and scanning transmission electron microscopy (STEM) cross sections, they show that the silicon thickness oxidized during the Si3N4 etching decreases from 1.5 nm in CW to 0.5 using a plasma pulsed at 1 kHz and 10% duty cycle, and the percentage of carbon implanted into the silicon substrate is reduced by a factor 2 using pulsed plasma conditions. Moreover, STEM cross sections show an improvement of the spacer profile when the plasma is pulsed at 1 kHz and low duty cycles, with a rounded spacer top leading to a better gate encapsulation, instead of the faceted spacer obtained using CW plasma conditions.

2-D Modeling Capability Certification of Optical Critical Dimension (OCD) Metrology Tool by Sigma Shape PMOS Silicon Recess Structure

Optical Critical Dimension (OCD) metrology is a much popular and efficient way to monitor structure sizes such as heights, side wall angles (SWAs), and critical dimensions (CDs). Due to the continuous shrinkage of feature sizes, the IC process is becoming more and more complicated. The growing demand on the OCD applications always outpaces the development of OCD-technology capabilities. Thus, we have to find a more reliable method and a special structure to certify the capability of OCD modeling and library stability, so as to improve the measurement performance as much as possible. In this paper, we selected a 2-D Sigma Shape PMOS Silicon Recess (Σ-PSR) structure for the OCD modeling evaluation and established a certification procedure as well as a relevant evaluation method, which includes the design of DOE (Design of Experiment) wafers, the handbook for data collections, the scoreboard for OCD result analysis for verifying both OCD 2-D modeling performance and library stability. The DOE wafers were processed to form different PSR structures such as total silicon recess depth, sigma height, pull back, tip-off-gate, undercut, and spacer width splits, etc. There are 17-output required parameters for the OCD modeling. At least, 9 floating parameters are necessary to build the Σ-PSR model. The accuracy of the DOE trend and the precision, stability, and GRR (Gauge Repeatability and Reproducibility) of all output parameters were analyzed to evaluate the capability of the OCD modeling. TEM data were also collected to demonstrate the OCD performance of Σ-PSR profile monitor. Finally, we summarized the evaluation method and discussed the future OCD certification work by advanced reference metrology tools.

Patterning of silicon nitride for CMOS gate spacer technology. I. Mechanisms involved in the silicon consumption in CH3F/O2/He high density plasmas

A loss of silicon in active source/drain regions of CMOS transistors can be observed during nitride spacer etch processes, employing CH3F/O2/He based chemistries in high density plasmas. This phenomenon, the so-called “silicon recess”, is a key criterion for the subsequent steps involved in the transistor fabrication process. In this work, the authors compare two CH3F/O2/He spacer etch processes typically used in industry. The mechanism for high Si3N4/Si selectivity is identified as the creation of a SiOxFy passivation layer, generated at the silicon surface. Using in situ ellipsometry and angle resolved x-ray photoelectron spectroscopy, the authors demonstrate that the oxidized layer which leads to silicon recess is driven by the ion energy. Moreover, in the case of high ion energy processes, implanted carbon has been identified under the SiOxFy passivation layer.

A Study of Sigma-Shaped Silicon Trench Formation

The strict shape control of sigma-shaped silicon trench has to leverage the dry etch process coupled with the appropriate post-etch treatment (PET). Here we addressed the strong link between the shape of dry etch based silicon recess and its effect on the definition of final sigma-shaped trench. Experiment results indicate the critical physical parameters of final sigma-shape silicon trench could be predicted by means of geometry analysis and monitoring dry etching related recess in bulk silicon. Besides, we also noticed the effect of pattern-dependent depth loading at dense areas. Organic polymer generated during etch process tends to introduce the trench depth variation. Polymer lean etch process has been proven as one of effective knobs to overcome such loading to some extent. In addition, the oxidation capacity of post-etch treatment can not be ignored. The ultra-thin silicon oxide film on silicon trench sidewall must be completely removed by dilute hydrofluoric acid before PET to avoid the possible trench depth loading.

Silicon recess minimization during gate patterning using synchronous plasma pulsing

With the emergence of new semiconductor devices and architectures, there is a real need to limit plasma induced damage. This study clearly demonstrates the capability of pulsed plasma technology to minimize plasma induced silicon oxidation that leads to the silicon recess phenomenon during polysilicon gate patterning. Indeed, the authors show that by pulsing optimized continuous wave overetch plasma conditions using HBr/He/O2 plasmas, the silicon recess is reduced from 0.6 to 0.2 nm, while the gate profiles are maintained anisotropic. Synchronous pulsed plasmas open new paths to pattern complex stacks of ultrathin materials without surface damage.

A Study of Dry Etching Process for Sigma-Shaped Si Recess

The fabrication of sigma-shaped silicon recess normally consists of dry etch process to shape the silicon trench and post etch treatment to form the sigma-shaped cavity within bulk silicon substrate. Here we are dedicated to the optimization of silicon recess dry etch process and its effect on the final sigma-shaped SiGe physical performance. Results show the isotropic ratio of horizontal over vertical direction could be doubled. This caters much larger process window for the desired strain introduction at the hetero-junction of SiGe/Si. Besides, the corresponding dry etching solutions are also disclosed from the point of view of tip depth adjustment and tip horizontal pull-back control. Both physical indexes could be independently controlled to deliver the required sigma-shaped Si recess trench.

OCD Metrology Evaluation of p-MOS Silicon Recess with Three Dimensional Design Pattern

OCD metrology has been proven to be a fast, accurate, and non-destructive knob for in-situ monitoring of line width and profile. In order to main Moore's law, device dimension is moving towards 45nm technology node and beyond, it is becoming increasingly difficult to perform the in-situ evaluation for those complicated structures by either CD-SEM or AFM. In this work, we come up with one specific 3D pattern to realize the 3D monitoring of p-MOS silicon recess (PSR) etch performance. The corresponding OCD library was identified and implemented on Nova OCD 3090 next. Several key floating parameters include PSR & STI depth, gate & AA CD, nitride spacer width and SWA. Good CD correlation between OCD and CD-SEM is obtained on the same 3D pattern. Consistent trench depth match is also observed between OCD and blanket pattern based AFM. Besides, dynamic repeatability test shows the acceptable reliability for 3D PSR OCD monitoring as well.

Modeling of plasma-induced damage and its impacts on parameter variations in advanced electronic devices

A comprehensive model predicting the effects of plasma-induced damage (PID) on parameter variations in advanced metal–oxide–semiconductor field-effect transistors (MOSFETs) is proposed. The model focuses on the silicon recess structure (Si loss) in the source/drain extension region formed by high-energy ion bombardment during plasma etching. The model includes the following mechanisms: (1) damaged layer formation by ion impact and penetration, (2) Si recess structure formation by a subsequent wet etch, (3) MOSFET performance degradation, and (4) MOSFET parameter variation. Based on a range theory for plasma-etch damage, the thickness of the damaged layer exhibits a power-law dependence on the energy of the ion incident on the surface of Si substrate. Assuming that the damaged layer was formed during a gate or an offset spacer etch process, the depth of Si recess (dR) is a function of the depth profile of the created defect site (ndam), the wet-etch stripping time (tw), and the energy of the incident ion. It was found that dR also showed a power-law dependence on the average ion energy E−ion estimated from applied self-dc-bias voltage for various tw. As for MOSFET performance degradation, the threshold voltage (Vth) shifted and the shift (ΔVth) increased with an increase in E−ion and a decrease in gate length. This induces an increase in subthreshold leakage current (Ioff) for MOSFET. Technology computer-aided-design simulations were performed to confirm these results. By integrating the presented PID models, parameter variations could be predicted: Using a Monte Carlo method, it was demonstrated that PID increases parameter variations such as Vth and Ioff. It also was found that the variation in E−ion induces Vth and Ioff variations, comparable to that induced by other process parameter fluctuations such as dopant fluctuation and gate length. In summary, considering the effects of PID on parameter variations is vital for designing future ultralarge-scale-integrated circuits with billions of built-in MOSFETs.

Synchronous Pulsed Plasma for Silicon Etch Applications

This paper investigates the interest of synchronous pulsed plasmas to etch silicon in HBr/O2 chemistries. Using mass spectrometry, ellipsometry and angle resolved X-ray photoelectron spectroscopy, we demonstrate that the radical concentration in the plasma, the etch rate and formation of passivation layers, can be controlled by the RF pulse parameters (frequency and duty cycle). Accordingly, pattern profiles are improved, selectivity to the mask is increased and the silicon recess is reduced from 4 to 0.8 nm when the HBr/O2 plasma lands on thin silicon oxide.

Reducing damage to Si substrates during gate etching processes by synchronous plasma pulsing

Plasma oxidation of the c-Si substrate through a very thin gate oxide layer can be observed during HBr/O2/Ar based plasma overetch steps of gate etch processes. This phenomenon generates the so-called silicon recess in the channel and source/drain regions of the transistors. In this work, the authors compare the silicon recess generated by continuous wave HBr/O2/Ar plasmas and synchronous pulsed HBr/O2/Ar plasmas. Thin SiO2 layers are exposed to continuous and pulsed HBr/O2/Ar plasmas, reproducing the overetch process conditions of a typical gate etch process. Using in situ ellipsometry and angle resolved X-ray photoelectron spectroscopy, the authors demonstrate that the oxidized layer which leads to silicon recess can be reduced from 4 to 0.8 nm by pulsing the plasma in synchronous mode.

Interplay of plasma etch, strip and wet clean in patterning La 2O 3/HfO 2-containing high-κ/metal gate stacks

The removal process of the La 2O 3/HfO 2 dielectric and of the residues after metal gate etch are discussed. The challenges are presented and related to the specific physico-chemical properties of La-containing compounds. Solutions based on optimization of plasma etch, strip and wet clean are demonstrated for both an integrated and delayed etch–clean process. Both processes meet the stringent requirements of complete removal of the high-κ layers and metal-containing sidewall residues without inducing silicon recess or undercut.

Interplay between Dry Etch and Wet Clean in Patterning La2O3/HfO2 Containing High-k/metal Gate Stacks

A dry-wet patterning process for La2O3/HfO2-containing high-κ/ metal gate stacks was successfully developed. The process meets the stringent requirements of complete removal of the high-κ layers and metal-containing sidewall residues without inducing silicon recess or undercut. The interaction between the dry etch and wet clean steps was studied. Use of a BCl3-based plasma process facilitated the cleaning process as it damages and modifies the high-κ layers in the active area. When the dry etch process ends with a BCl3-step, La-containing residues were formed inhomogeneously over the wafer within the time scale of hours. These residues could no longer be removed with a wet clean, but were not observed when the dry etch and wet clean processes were integrated. This demonstrates that an integrated etch-clean process enlarges the process window.

Three Series-Connected Transistor Model for a Recess-Channel-Array Transistor and Improvement of Electrical Characteristics by a Bottom Fin Structure

A three series-connected transistor model is introduced to understand the electrical characteristics of conventional recess-channel-array transistors (RCATs) and modified RCATs. An RCAT is considered to be a serial connection of three transistors consisting of one bottom transistor and two vertical transistors. The electrical characteristics of a cell transistor are explained by a balance of those transistors. A newly modified fin-RCAT which has a fin structure at the bottom of a silicon recess is proposed to improve cell transistor characteristics. This design improves cell current by 70% while maintaining retention characteristics.

Notching characteristics of un-doped amorphous silicon in high density plasma etching

Notching in un-doped amorphous silicon gate etching, a profile distortion phenomenon, has been studied and analyzed with low pressure, high density plasmas using HBr/Cl 2/O 2 chemistries. In contrast with the notching phenomenon observed in doped polysilicon etching, a notch was evolved at the outer sidewall foot of the edge line, where the outer sidewall of the edge line was exposed to a microscopic open area. A considerable recess was observed at the upper corner of a trench etched silicon substrate in photoresist-masked gate etching, while an oxynitride-masked gate structure showed little silicon recess at the same region. The subsequent accumulation of ions caused by deflected ions on the oxide surface adjacent to the outermost gate line leads to the formation of a local electric field near the outermost gate line, intensifying the ion trajectory distortion toward the sidewall foot of the outermost gate line.

Evaluation of Plasma Strip Induced Substrate Damage

High dose, ultra shallow junction implant resist strip requires minimal substrate loss and dopant loss. Silicon recess (silicon loss) under the source/drain (S/D) extensions increases the S/D extension resistance and decreases drive currents by changing the junction profile. ITRS surface preparation technology roadmap [1] targets silicon loss to be 0.4Å per cleaning step for 45nm and 0.3Å for 32nm generation. Fluorine-containing chemistries which are often used to enhance implanted resist strip and residue removal result in unacceptable substrate loss. A non-fluorine plasma strip was developed in earlier work and is qualified for 45nm logic production [2]. The objective of this work is to study the substrate damage that is induced by the resist strip plasma process. Silicon surface oxidation and silicon loss of different plasma strip chemistries were evaluated with various metrologies such as optical ellipsometry, electrical oxide measurement, XPS, TEM and mass measurement. The impact of different strip chemistries on dopant retention and distribution is also discussed.

Stripping and Cleaning of High-Dose Ion-Implanted Photoresists Using a Single-Wafer, Single-Chamber Dry/Wet Hybrid System

Stripping high-dose ion-implanted (HDI) photoresists is considered as one of the most challengeable processes in the semiconductor manufacturing due to the difficulty of both removing crust (or carbonized layer) formed during the ion implantation and preventing the silicon recess after subsequent cleaning. The HDI photoresists are conventionally removed by using a two-step process, low-pressure plasma ashing in a single-wafer tool followed by SPM-based wet stripping in a batch immersion tool. Alternative HDI-resist strip methods have been proposed, such as a combination of physical-force pretreatments followed by more traditional wet cleaning steps [1], a SPM-based all-wet process at extremely high temperature (≥ 200°C) [2], and supercritical CO2 combined with chemical additive formulations [3].

Study on silicon surface oxidation of post-implant resist cleaning

Minimum substrate loss is required for resist strip of high dose, ultra shallow junction implant for source/drain extensions. Silicon surface oxidation of downstream plasma resist strip results in silicon recess of the source/drain extension regions. This paper reports the study of silicon surface oxidation for different resist strip plasma chemistries and the effect of plasma strip process parameters such as power, pressure and temperature on silicon surface oxidation. A good agreement was found between optical ellipsometry, XPS (X-ray photoelectron spectroscopy) and TEM (transmission electron spectroscopy) for thickness measurement of very thin (<20 Å) oxide grown on silicon surface due to plasma exposure. Selectivity of crust breakthrough and resist removal over silicon oxidation was also discussed in this paper along with dopant loss.

On the interest of carbon-coated plasma reactor for advanced gate stack etching processes

In integrated circuit fabrication the most wide spread strategy to achieve acceptable wafer-to-wafer reproducibility of the gate stack etching process is to dry-clean the plasma reactor walls between each wafer processed. However, inherent exposure of the reactor walls to fluorine-based plasma leads to formation and accumulation of nonvolatile fluoride residues (such as AlFx) on reactor wall surfaces, which in turn leads to process drifts and metallic contamination of wafers. To prevent this while keeping an Al2O3 reactor wall material, a coating strategy must be used, in which the reactor is coated by a protective layer between wafers. It was shown recently that deposition of carbon-rich coating on the reactor walls allows improvements of process reproducibility and reactor wall protection. The authors show that this strategy results in a higher ion-to-neutral flux ratio to the wafer when compared to other strategies (clean or SiOClx-coated reactors) because the carbon walls load reactive radical densities while keeping the same ion current. As a result, the etching rates are generally smaller in a carbon-coated reactor, but a highly anisotropic etching profile can be achieved in silicon and metal gates, whose etching is strongly ion assisted. Furthermore, thanks to the low density of Cl atoms in the carbon-coated reactor, silicon etching can be achieved almost without sidewall passivation layers, allowing fine critical dimension control to be achieved. In addition, it is shown that although the O atom density is also smaller in the carbon-coated reactor, the selectivity toward ultrathin gate oxides is not reduced dramatically. Furthermore, during metal gate etching over high-k dielectric, the low level of parasitic oxygen in the carbon-coated reactor also allows one to minimize bulk silicon reoxidation through HfO2 high-k gate dielectric. It is then shown that the BCl3 etching process of the HfO2 high-k material is highly selective toward the substrate in the carbon-coated reactor, and the carbon-coating strategy thus allows minimizing the silicon recess of the active area of transistors. The authors eventually demonstrate that the carbon-coating strategy drastically reduces on-wafer metallic contamination. Finally, the consumption of carbon from the reactor during the etching process is discussed (and thus the amount of initial deposit that is required to protect the reactor walls) together with the best way of cleaning the reactor after a silicon etching process.