Silicon Photonic Receiver Research Articles

Instantaneous Material Classification Using a Polarization-Diverse RMCW LIDAR.

Light detection and ranging (LIDAR) sensors using a polarization-diverse receiver are able to capture polarimetric information about the target under measurement. We demonstrate this capability using a silicon photonic receiver architecture that enables this on a shot-by-shot basis, enabling polarization analysis nearly instantaneously in the point cloud, and then use this data to train a material classification neural network. Using this classifier, we show an accuracy of 85.4% for classifying plastic, wood, concrete, and coated aluminum.

Non-Sliced Optical Arbitrary Waveform Measurement (OAWM) Using a Silicon Photonic Receiver Chip

Non-Sliced Optical Arbitrary Waveform Measurement (OAWM) Using a Silicon Photonic Receiver Chip

Continuous-variable quantum key distribution over 28.6 km fiber with an integrated silicon photonic receiver chip

Quantum key distribution, which ensures information-theoretically secret key generation, is currently advancing through photonic integration to achieve high performance, cost reduction, and compact size, thereby facilitating the large-scale deployment. Continuous-variable quantum key distribution is an attractive approach for photonic integrations due to its compatibility with off-the-shelf optical communication devices. However, its chip-based systems have encountered significant limitations primarily related to the shot-noise-limited receiver design, which demands low noise, wide bandwidth, high clearance, and well stability. Here, we report the implementation of a real local oscillator continuous-variable quantum key distribution system with an integrated silicon photonic receiver chip. Thanks to the well-designed chip-based homodyne detectors with a bandwidth up to 1.5 GHz and a clearance up to 7.42 dB, the transmission distance of the system has been extended to 28.6 km, achieving a secret key generation rate of Mbps level. This technological advancement enables the quantum key distribution systems with photonic integrated receivers to achieve the coverage in both access network scenarios and short-distance metropolitan interconnections, paving the way for the development of the next-generation quantum key distribution networks on a large scale.

A 25-Gb/s 3-D Direct Bond Silicon Photonic Receiver in 12-nm FinFET

A 25-Gb/s 3-D Direct Bond Silicon Photonic Receiver in 12-nm FinFET

A 20–43.5-GHz Wideband Tunable Silicon Photonic Receiver Front-End for mm-wave Channel Selection/Jammer Rejection

This article presents a 20–43.5-GHz mm-wave silicon photonic reconfigurable receiver (RX) front-end (FE) for wideband mm-wave 5G systems. The wideband front-end consists of an input electro-optic (E/O) converter, a silicon photonic integrated circuit (PIC), and an output opto-electric (O/E) converter. The silicon PIC is programmable either as a mm-wave band-pass filter (BPF) for channel selection and jammer rejection or as a mm-wave notch filter for jammer rejection in adjacent and alternate channels. Both the BPF and notch filter center frequencies are continuously tunable over a 20- and 43.5-GHz range, with the BPF bandwidth also configurable between 4.7-6-GHz. In order to show the effect of in-band jammer rejection on improving system linearity and overall received signal quality, a 4-channel system is demonstrated with the BPF configured with 5-GHz 3-dB bandwidth. The whole mm-wave system is optimized for minimum noise figure ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$NF$</tex-math></inline-formula> ), maximum linearity (third-order input intercept point ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$IIP_{3}$</tex-math></inline-formula> ) and input 1-dB compression power ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$IP_{\text{1}\,\text{dB}}$</tex-math></inline-formula> ), and maximum signal to noise ratio (SNR) through modulator bias control and optical amplification. An IM <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$_{3}$</tex-math></inline-formula> reduction, and thus IIP <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$_{3}$</tex-math></inline-formula> improvement, of 22.5- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$\text{dB}$</tex-math></inline-formula> is achieved. This yields an average error vector magnitude (EVM) improvement of 4.5- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$\text{dB}$</tex-math></inline-formula> at 20-GHz and 50- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$\text{Msps}$</tex-math></inline-formula> 16-quadrature amplitude modulation (16-QAM), with an overall EVM of −25.5- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$\text{dB}$</tex-math></inline-formula> . To the best of the authors' knowledge, this is the first silicon photonic implementation of a wideband reconfigurable mm-wave RX that covers the entire mm-wave sub-45-GHz band.

Polarization-independent wavelength demultiplexer based on a single etched diffraction grating device

Polarization-compatible receivers are indispensable in transceivers used for wavelength division multiplexing optical communications, as light polarization is unpredictable after transmission through network fibers. However, the strong waveguide birefringence makes it difficult to realize a polarization-independent wavelength demultiplexer in a silicon photonic receiver. Here, we utilized the birefringence effect for simultaneously demultiplexing wavelengths and polarizations, and experimentally demonstrated a polarization-independent wavelength demultiplexer with a single device on a SiPh platform. The principle was validated on an etched diffraction grating, which successfully split the arbitrarily polarized light containing four wavelengths into eight channels with single-polarization and single-wavelength signals. Polarization-dependent losses of 0.5–1.8 dB, minimum insertion loss of 0.5 dB, and crosstalks lower than −30 dB were experimentally measured for the fabricated etched diffraction grating. Thus, a promising general solution was developed for implementing polarization-independent wavelength division multiplexing receivers and other polarization-independent devices on photonics platforms with birefringent waveguide devices.

Experimental demonstration of a 160 Gbit/s 3D-integrated silicon photonics receiver with 1.2-pJ/bit power consumption.

By using the flip-chip bonding technology, a high performances 3D-integrated silicon photonics receiver is demonstrated. The receiver consists of a high-speed germanium-silicon (Ge-Si) photodetector (PD) and a commercial linear transimpedance amplifiers (TIA). The overall 3 dB bandwidth of the receiver is around 38 GHz with appropriate gain. Based on this 3D-integrated receiver, the 56, 64, 90, 100 Gbit/s non-return-to-zero (NRZ) and 112, 128 Gbit/s four-level pulse amplitude (PAM-4) modulation clear openings of eye diagrams are experimentally obtained. The sensitivities of -10, -5.2 dBm and -6.6, -2.7 dBm were obtained for 112 Gbit/s NRZ and 160 Gbit/s PAM-4 at hard-decision forward err correction (HD-FEC,3.8 × 10-3) and KP4 forward err correction (KP4-FEC,2 × 10-4) threshold, respectively. Additionally, the lowest power consumption of this receiver is about 1.2 pJ/bit, which implies its huge potential for short-reach data center applications.

Silicon photonic receiver for satellite laser communication terminals.

We report the optical performance of a photonic receiver for laser communication applications. The receiver is composed of 14 × 12 grating coupler arrays. The received optical signal power will be combined electrically via germanium photodiodes. The photonic receiver is designed for 20-µm to 30-µm mode field diameter (MFD) input sources. To maximize the fill factor of the 200 µm × 200 µm light-receiving area, a design strategy has been proposed. (1) Grating couplers are customized for compactness. (2) Periods of grating couplers are designed to work as end-fire and back-fire grating couplers for the same incident angle of the input laser source. (3) Different widths of waveguides are routed to minimize cross talk. The photonic receiver is evaluated with a 10-µm MFD source. As a result of the evaluation, the receiving area considering the minimum efficiency of -10.5 dB is 95% of the designed area when illuminating 20-µm to 300-µm MFD laser sources.

112 Gb/s PAM-4 Silicon Photonics Receiver Integrated With SiGe-BiCMOS Linear TIA

We have developed a silicon photonics receiver integrated with a SiGe-BiCMOS linear transimpedance amplifier (TIA) using the flip-chip bonding technology to assist in resolving the I/O bottleneck problem in inter-chip data communication. The proposed device demonstrated optical 112 Gb/s four-level pulse amplitude modulation (PAM-4) operations and clear eye openings without any equalization for the pseudorandom binary sequence <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$2^{\mathbf {15}}$ </tex-math></inline-formula> – 1 signal. The 3 dB bandwidth and transimpedance gain were designed to be 37.1 GHz and 60.1 dB <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\boldsymbol {\Omega } $ </tex-math></inline-formula> , respectively, at a supply voltage of 3.3 V. The consumption current of the linear TIA was 95.1 mA, and it resulted in a power consumption of 314 mW (2.8 pJ/bit). A linear TIA circuit is a key technology for PAM-4 operation; therefore, we discussed the linearity of our receiver response through eye diagrams and simulation. The measured eye diagrams agreed with the simulation results, and the proposed device maintained a linear response for up to 450 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\boldsymbol {\mu }\text{A}_{\mathbf {p-p}}$ </tex-math></inline-formula> input current. In addition, its operation rate of 112 Gb/s is the highest operation rate reported for a silicon photonics PAM-4 receiver based on flip-chip 3D integration with a germanium photodetector and a SiGe-BiCMOS linear TIA.

Pulse-Width-Modulation-Based Silicon Photonics Receiver with Readout Circuitries for On-chip Optical Power Monitoring

In this paper, a pulse-width-modulation (PWM)-based silicon photonics receiver for optical power monitoring that was realized using a 90-nm CMOS silicon-on-insulator (SOI) process is reported. By monitoring the DC or the AC power in the optical nodes and converting it into an electrical signal, large-scale photonic integrated circuits can acquire smartness and automation characteristics. The proposed PWM-based silicon photonics receiver can simply readout the optical power of target nodes without complex mixed-mode circuitries, such as analog-to-digital converters. The PWM receiver consists of a I–V amplifier, simple digital circuitries, free-running on-chip oscillators, and bias circuits. The receiver achieves a 10-nA detection limit, under a 1.5% detection error due to the quantization process of the PWM scheme. The receiver can operate as an on-chip optical power monitor for large-scale silicon-based photonic integrated circuits.

Multi-Rate Low-Noise Optical Receiver Front-End

Conventional optical receivers are mostly optimized for single data rate. In this work, after examining conventional optical front-ends, we present the low-noise tunable front-end (LNTF) topology, which is able to achieve optimized noise performance at multiple data rates. In addition, colored noise optimization techniques including capacitive noise scaling and CMOS inverter based transimpedance amplifier (TIA) are also studied, which together with the LNTF form a low-noise design methodology for silicon photonics based CMOS optical receiver. Employing these techniques, the implemented 3D hybrid-integrated silicon photonics receiver achieves excellent noise performance of 0.91 μArms and 0.5 μArms input-referred noise current at 25 and 10 Gb/s, respectively, which enables high sensitivity of −14.6 dBm and −16.5 dBm OMA at BER = 10−12, correspondingly.

Co-design of a differential transimpedance amplifier and balanced photodetector for a sub-pJ/bit silicon photonics receiver.

This paper presents the design and implementation of a fully differential optical receiver, which is aimed for short reach intensity modulation and direct detection (IMDD) transceiver links. A Si-Ge balanced photodetector (PD) has been co-designed and packaged with a novel differential transimpedance amplifier (TIA). The TIA design is realized with a standard 28 nm CMOS process and operates with a standard digital supply (1V). Without using any equalization or DSP techniques, the proposed receiver can operate up to 54 Gb/s with a BER less than the KP4 limit (2.2×10-4) under an optical modulation amplitude (OMA) of -8.6 dBm, while the power efficiency has been optimized to 0.55 pJ/bit (0.98 pJ/bit if output buffer is included).

A 26-Gb/s 3-D-Integrated Silicon Photonic Receiver in BiCMOS-55 nm and PIC25G With −15.2-dBm OMA Sensitivity

This letter presents a 3-D-integrated 26 Gb/s opto-electrical receiver front-end. The electronic integrated circuit (EIC) is fabricated in a BiCMOS-55-nm technology, flipped and placed on top of the photonic integrated circuits (PICs) die through copper pillars. In the receiver chain, a fully differential shunt-feedback TI amplifier (FD-SF TIA) is followed by a limiting amplifiers (LAs) with embedded equalization, output driver and an automatic offset cancelation loop. The whole receiver provides a transimpedance (TI) gain of 76 dBΩ with 30-GHz bandwidth. By exploiting the FD-SF TIA with low parasitic capacitance of the Germanium dual heterojunction photo diode (Ge-PD) in the photonic die, the receiver achieves sensitivity of -15.2 dBm optical modulation amplitude (OMA) at Ge-PD and -10-dBm OMA at the single-mode fiber (SMF) optical output with bit error rate of 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-12</sup> and PRBS 15. The sensitivity is aligned with state-of-the-art receivers employing discrete photonics and, to author's best knowledge, it is the lowest reported among published 25 Gb/s receivers exploiting silicon photonics.

25 × 50 Gbps wavelength division multiplexing silicon photonics receiver chip based on a silicon nanowire-arrayed waveguide grating

A high-performance monolithic integrated wavelength division multiplexing silicon (Si) photonics receiver chip is fabricated on a silicon-on-insulator platform. The receiver chip has a 25-channel Si nanowire-arrayed waveguide grating, and each channel is integrated with a high-speed waveguide Ge-on-Si photodetector. The central wavelength, optical insertion loss, and cross talk of the array waveguide grating are 1550.6 nm, 5–8 dB, and −12–−15 dB, respectively. The photodetectors show low dark current density of 16.9 mA/cm2 at −1 V and a high responsivity of 0.82 A/W at 1550 nm. High bandwidths of 23 and 29 GHz are achieved at 0 and −1 V, respectively. Each channel can operate at 50 Gbps with low input optical power even under zero bias, which realizes an aggregate data rate of 1.25 Tbps.

Multi-channel silicon photonic receiver based on compact second-order microring resonators

A monolithically integrated multi-channel receiver fabricated on the Silicon-on-Insulator (SOI) platform is demonstrated experimentally. This receiver is composed of an eight-channel thermally tunable microring resonator (MRR) filter as the wavelength division multiplexing (WDM) demultiplexer and an array of high speed waveguide-integrated Ge-on-Si photodetectors (PDs) for light detection. Second-order MRRs were utilized in each channel to obtain steeper roll-off from passband to stopband and lower crosstalk. The receiver was fabricated by using CMOS-compatible fabrication process at IME A*STAR. With the thermal tunability, the channel spacing can be adjusted according to different channel grid. Lower than −30 dB crosstalk and higher than 50 GHz 3-dB bandwidth was obtained for the demultiplexer with a channel spacing of 150 GHz. Proof-of-principle demonstration shows that each channel is capable of operating at a data rate of 10 Gb/s, resulting in an aggregate data rate of 80 Gb/s.

8-channel WDM silicon photonics transceiver with SOA and semiconductor mode-locked laser.

We demonstrate an integrated 8 by 14 Gbps dense wavelength division multiplexed silicon photonics transceiver that makes use of an external mode-locked laser as a light source and a single semiconductor optical amplifier for post-modulation signal amplification. Remaining components necessary for modulation, filtering and (de‑)multiplexing are monolithically integrated in a single chip. In all system experiments, all eight channels are jointly operated with independent data streams in order to include impairments arising out of nonlinear effects inside the SOA while benchmarking the system performance. The transmitter, measured with a commercial reference receiver, supports on-off keying data transmission with an uncorrected BER ranging between 1e-5 and 5e-7 for all channels in back-to-back configuration and between 8e-4 and 1e-5 after 10 km transmission (both PRBS 231-1). The three best channels of the full link consisting in the silicon photonics transmitter operated with the silicon photonics receiver in back-to-back configuration maintain a BER better than the targeted 5e-5. Based on link budget modeling, we expect this target to be reached for all 8 channels pending improvement of the receiver offset compensation loop.

Compact Low-Power-Consumption 28-Gbaud QPSK/16-QAM Integrated Silicon Photonic/Electronic Coherent Receiver

We demonstrate the codesign and cointegration of an ultracompact silicon photonic receiver and a low-power-consumption (155 mW/channel) two-channel linear transimpedance amplifier array. Operation below the forward error coding (FEC) threshold both for quadrature phase-shift keying (QPSK) and 16-quadrature amplitude modulation (QAM) at 28 Gbaud is demonstrated.

A 25-Gb/s 5 × 5 mm2Chip-Scale Silicon-Photonic Receiver Integrated With 28-nm CMOS Transimpedance Amplifier

We have developed a 5 × 5 mm2 compact silicon-photonic receiver with a 28-nm CMOS transimpedance-amplifier (TIA) chip. The receiver chip was designed using a photonics—electronics convergence design technique for the realization of high-speed and high-efficiency operation because the interfaces of the optical and electrical components greatly influence the receiver characteristics. Optical pins were used to obtain easy optical alignment between the multimode fibers and the germanium photodetectors. An aluminum stripline between the PD and the TIA enhanced the 3-dB bandwidth because its characteristic impedance is greater than the TIA input impedance. Coplanar waveguides (CPWs) on the etched SOI wafer achieved a low insertion loss because the overlap between the electric fields of the CPWs and the silicon layer was reduced. We demonstrated 25-Gb/s error-free operation at both 25 and at 85 °C. The minimum sensitivities and power consumptions of the receivers were −11.0 dBm and 2.3 mW/Gb/s at 25 °C and −10.2 dBm and 2.5 mW/Gb/s at 85 °C, respectively. These results show that our receiver can be applied for practical use at high temperatures.

A 40 Gb/s Monolithically Integrated Linear Photonic Receiver in a &lt;formula formulatype="inline"&gt;&lt;tex Notation="TeX"&gt;$0.25~\mu {\rm m}$&lt;/tex&gt;&lt;/formula&gt; BiCMOS SiGe:C Technology

This letter presents the first 40 Gb/s monolithically integrated silicon photonics linear receiver (Rx) comprising a germanium photodiode (Ge-PD) and a linear transimpedance amplifier (TIA). Measured optical-electrical (O/E) 3 dB bandwidth (BW) of the Rx is 31 GHz. At 40 Gb/s, the Rx achieves a sensitivity of $-3~{\rm dBm}$ average optical input power with BER of $2.5\times 10^{-11}$ . It operates at $\lambda =1.55 ~\mu{\rm m}$ wavelength, uses 3.3 and 3.7 V power supplies, dissipates 275 mW of power, provides maximum differential output amplitude of $500 ~{\rm mV}_{\rm pp}$ , and occupies an area of $3.2~{\rm mm}^{2}$ . The presented receiver achieves the highest bit rate among the published work in monolithically integrated silicon photonics receivers.

Silicon photonic receiver and transmitter operating up to 36 Gb/s for λ~1550 nm.

We present the hybrid-integrated silicon photonic receiver and transmitter based on silicon photonic devices and 65 nm bulk CMOS interface circuits operating over 30 Gb/s with a 10(-12) bit error rate (BER) for λ ~1550nm. The silicon photonic receiver, operating up to 36 Gb/s, is based on a vertical-illumination type Ge-on-Si photodetector (Ge PD) hybrid-integrated with a CMOS receiver front-end circuit (CMOS Rx IC), and exhibits high sensitivities of -11 dBm, -8 dBm, and -2 dBm for data rates of 25 Gb/s, 30 Gb/s and 36 Gb/s, respectively, at a BER of 10(-12). The measured energy efficiency of the Si-photonic receiver is 2.6 pJ/bit at 25 Gb/s with an optical input power of -11 dBm, and 2.1 pJ/bit at 36 Gb/s with an optical power of -2 dBm. The hybrid-integrated silicon photonic transmitter, comprised of a depletion-type Mach-Zehnder modulator (MZM) and a CMOS driver circuit (CMOS Tx IC), shows better than 5.7 dB extinction ratio (ER) for 25 Gb/s, and 3 dB ER for 36 Gb/s. The silicon photonic transmitter achieves the data transmission with less than 10(-15) BER at 25 Gb/s, 10(-14) BER at 28 Gb/s, and 6 x 10(-13) BER with the energy efficiency of ~6 pJ/bit at 30 Gb/s.