Silicon Overhead Research Articles

DICEguard: enhancing DICE security for IoT devices with periodic memory forensics

The number of Internet-of-Things (IoT) devices has been increasing rapidly every year. Most of these devices have access to important personal data such as health, daily activities, location, and finance. However, these devices have security problems since they have limited processing power and memory to implement complex security measures. Therefore, they possess weak authentication mechanisms and a lack of encryption. Additionally, there are no widely accepted standards for IoT security. Device Identifier Composition Engine (DICE) was proposed as a standard that enables adding a security layer to low-cost microcontrollers with minimal silicon overhead. However, previous studies show that DICE-based attestation is vulnerable to some remote attacks. In this study, we present a novel method called DICEguard to address the security problems of DICE. One of the key innovations of DICEguard is its incorporation of periodic memory forensics (PMF) technique, leveraging a hardware-based hash engine to detect and mitigate potential security breaches resulting from firmware vulnerabilities. DICEguard enhances the overall resilience of IoT devices against attacks by swiftly detecting alterations indicative of malicious activity through periodic calculation and comparison of firmware digests. Furthermore, DICEguard introduces a one-time programmable (OTP) memory component to safeguard critical security parameters, such as public keys used for signature verification, against tampering by adversaries. This ensures the integrity of essential security measures even in the face of sophisticated attacks. We implemented the enhanced DICE architecture using the open-source RISC-V platform Ibex and the mbedTLS library for cryptographic operations. We performed the hash operations required by DICE in a hardware-based manner on a commercial Field Programmable Gate Array (FPGA) platform rather than firmware, which is more vulnerable to attacks. Our test results show that with negligible area overhead to a standard microcontroller system, the proposed method can detect the simulated attacks.

Alphanumeric Pattern Recognition by Memristive Crossbar Circuit using Perceptron Learning Rule

This paper presents an alphanumeric pattern recognition approach based on memristive crossbar circuit using perceptron learning rule. The proposed approach incorporates a memristive crossbar-based learning and training circuit (TC) module (i.e., synaptic network) and an operational amplifier (op-amp)-based neuron. Alphanumeric patterns, such as alphabets (A–Z) and numerics (0–9), are applied on the TC module and it adjusts the synaptic weights using the perceptron learning rule. The TC module includes 16 inputs, which are interconnected to nine output neurons through memristors. The input and output patterns are represented through [Formula: see text] and [Formula: see text] matrix pixels, respectively. This proposed circuit has implemented all alphanumeric patterns, such as alphabets (A–Z) and numerics (0–9), successfully. However, only the pattern “A” is illustrated in detail for better understanding. SPICE simulation results supported by analytical calculations of pattern “A” are reported. The average power consumption for the proposed approach using memristor is 77.77% lower than the conventional MOSFET-based approach, apart from significant saving of silicon overhead in contrast to its counterpart approach.

Reduction of Test Data with Hybrid Test Points

ATPG vectors for a combinational circuit exhibit correlations among the bits of a test vector. We propose a BIST circuit design methodology using spectral methods which utilizes the correlation information. This circuit serves dual purposes. It generates BIST vectors that are similar to the ATPG vectors with higher test coverage as compared to random and weighted random vectors. The same circuit can also function as a test data de-compressor for compressed ATPG vectors applied from an external tester. Logic built-in self-test (LBIST) is now increasingly used with on-chip test compression as a complementary solution for in-system test, where high quality, low power, low silicon area, and most importantly short test application time are key factors affecting ICs targeted for safety-critical systems. Test points, common in LBIST-ready designs, can help to reduce test time and the overall silicon overhead so that one can get desired test coverage with the minimal number of patterns. Typically, LBIST test points are dysfunctional when enabled in an ATPG-based test compression mode. Similarly, test points used to reduce ATPG pattern counts cannot guarantee desired random testability. We present a hybrid test point technology designed to reduce deterministic pattern counts and to improve fault detection likelihood by means of the same minimal set of test points. The hybrid test points are subsequently deployed in a scan-based LBIST scheme addressing stringent test requirements of certain application domains such as the automotive electronics market. These requirements, largely driven by safety standards, are met by significantly reducing test application time while preserving the high fault coverage. The new scheme is a combination of pseudorandom test patterns delivered in a test-per-clock fashion through conventional scan chains and per cycle-driven hybrid observation test points that capture faulty effects every shift cycle into dedicated scan chains. We also exhibit test data compression capabilities of the proposed BIST architecture. This architecture provides a maximum test data compression exceeding and a proportional test time reduction for serial interface reseeding.

Logic BIST With Capture-Per-Clock Hybrid Test Points

Logic built-in self-test (LBIST) is now increasingly used with on-chip test compression as a complementary solution for in-system test, where high quality, low power, low silicon area, and most importantly short test application time are key factors affecting ICs targeted for safety-critical systems. Test points, common in LBIST-ready designs, can help to reduce test time and the overall silicon overhead so that one can get desired test coverage with the minimal number of patterns. Typically, LBIST test points are dysfunctional when enabled in an ATPG-based test compression mode. Similarly, test points used to reduce ATPG pattern counts (PCs) cannot guarantee desired random testability. In this paper, we present a hybrid test point technology designed to reduce deterministic PCs and to improve fault detection likelihood by means of the same minimal set of test points. The hybrid test points are subsequently deployed in a scan-based LBIST scheme addressing stringent test requirements of certain application domains such as the automotive electronics market. These requirements, largely driven by safety standards, are met by significantly reducing test application time while preserving the high fault coverage. The new scheme is a combination of pseudorandom test patterns delivered in a test-per-clock fashion through conventional scan chains and per-cycle-driven hybrid observation test points that capture faulty effects every shift cycle into dedicated scan chains. Their content is gradually shifted into a compactor shared with the remaining chains that deliver responses once a test pattern has been shifted-in. Experimental results obtained for industrial designs confirm feasibility of the new schemes, and they are reported herein.

A PUF-based unified identity verification framework for secure IoT hardware via device authentication

In the era of Internet-of-Things (IoTs), millions of smart devices are interconnected and communicated through networks. To guarantee the security and reliability of data transmission in IoT, the underlying hardware of these devices must first be secure and trusted. However, due to the inherent mobility nature of current embedded devices, IoT hardware could be vulnerable to diverse security threats from multiple malicious participants. Among them, device theft is becoming one of the most challenging security issues that have incurred a serious impact on copyright. To effectively alleviate this threat, silicon physical unclonable function (PUF) has been presented and considered to be a reliable anti-piracy solution to complete the device authentication and key storage. However, current PUF solutions are mostly focused on chip-level verification and cannot provide systematic identification and authentication. To this end, this article proposes a unified identity verification framework which can provide fine-grained protection for embedded devices against theft attacks from the system level. This framework is established on a series of PUF circuits that have been implanted into each individual chip of the devices. We first improve the configurable ring oscillator (CRO) PUFs with the latch structure. Therefore, a unique sub-digital signature of each chip can be generated by performing the challenge-response strategy. We then reassemble all the sub-digital signatures and encode them to acquire the unique fingerprint of each embedded device, so as to achieve system-level device identification and authentication. Any substitution of an individual or all chips in the devices will result in the inconsistencies of the system-level fingerprint. We implement and verify the proposed scheme on the field programmable gate array (FPGA) platforms. Experimental results illustrate that the proposed framework can uniquely and accurately identify any or all of the thefts to the embedded system hardware at low silicon overhead.

A Parallel Digital VLSI Architecture for Integrated Support Vector Machine Training and Classification

This paper presents a parallel digital VLSI architecture for combined support vector machine (SVM) training and classification. For the first time, cascade SVM, a powerful training algorithm, is leveraged to significantly improve the scalability of hardware-based SVM training and develop an efficient parallel VLSI architecture. The presented architecture achieves excellent scalability by spreading the training workload of a given data set over multiple SVM processing units with minimal communication overhead. Hardware-friendly implementation of the cascade algorithm is employed to achieve low hardware overhead and allow for training over data sets of variable size. In the proposed parallel cascade architecture, a multilayer system bus and multiple distributed memories are used to fully exploit parallelism. In addition, the proposed architecture is rather flexible and can be tailored to realize hybrid use of hardware parallel processing and temporal reuse of processing resources, leading to good tradeoffs between throughput, silicon overhead and power dissipation. Several parallel cascade SVM processors have been designed with a commercial 90-nm CMOS technology, which provide up to a $561\times $ training time speedup and a significant estimated $21\,859\times $ energy reduction compared with the software SVM algorithm running on a 45-nm commercial general-purpose CPU.

Security enhancement of cloud servers with a redundancy-based fault-tolerant cache structure

The modern chip multiprocessors are vulnerable to transient faults caused by either on-purpose attacks or system mistakes, especially for those with large and multi-level caches in cloud servers. In this paper, we propose a modified/shared replication cache to keep a redundancy for the latest accessed and modified/shared L2 cache lines. According to the experiments based on Multi2Sim, this cache with proper size can provide considerable data reliability. In addition, the cache can reduce the average latency of memory hierarchy for error correction, with only about 20.2% of L2 cache energy cost and 2% of L2 cache silicon overhead.

An Optimal Memory BISR Implementation

Although integrated circuits (IC) shrink in size as the fabrication technology progresses, circuit designers always attempt to incorporate as much functionality as possible into a single die. Processor chips, particularly those used in data communications, are known to have the highest transistor density because they contain the highest percentage of embedded memories. In some cases, embedded memories occupy 50-80% of the die area. With inherently high density of memories, the manufacturing yield can become very poor even in a mature process. Also to keep the test cost affordable, having Built-In Self Tests (BIST) for memories is essential although testing would not improve the yield by itself. It has become a common practice to implement some type of memory repair scheme along with BIST in memory dominant IC designs. In this writing, such an integrated scheme is referred as Memory Built-In Self Repair (MBISR.) This paper elaborates a few practical criteria on designing and implementing built-in self-test circuits for testing and repairing a large number of embedded memories of different types and sizes in a single Integrated Circuit (IC). Various test architectures presented in this paper provide for different optimizing criteria such as test time, routing feasibility, silicon overhead, and dynamic power compliance. The repair circuits are based on the most popular and widely accepted built-in-self-test strategy, and are power aware, repair friendly, and supports scan based testing of random glue logic in SOC designs. These features are useful primarily in SOC testing because such designs typically contain many memories that are large but repairable. Without an effective repair scheme, the production yield of a SOC containing a large numbers of embedded memory types and instances may severely be compromised. We selected one of the optimizing criteria as the main objective, and made the relevant repair scheme implemented on a processor chip using a mature 0.18 micron process due to its low cost of fabrication. The repair scheme allowed self testing and repair at both wafer and package levels. We present the silicon data showing the actual Return On Yield (ROY) due to the built-in repair scheme when the repair scheme was dynamically controlled at test time.

Design and Implementation of an On-Chip Permutation Network for Multiprocessor System-On-Chip

This paper presents the silicon-proven design of a novel on-chip network to support guaranteed traffic permutation in multiprocessor system-on-chip applications. The proposed network employs a pipelined circuit-switching approach combined with a dynamic path-setup scheme under a multistage network topology. The dynamic path-setup scheme enables runtime path arrangement for arbitrary traffic permutations. The circuit-switching approach offers a guarantee of permuted data and its compact overhead enables the benefit of stacking multiple networks. A 0.13-μ m CMOS test-chip validates the feasibility and efficiency of the proposed design. Experimental results show that the proposed on-chip network achieves 1.9× to 8.2× reduction of silicon overhead compared to other design approaches.

Real-time fault injection using enhanced on-chip debug infrastructures

The rapid increase in the use of microprocessor-based systems in critical areas, where failures imply risks to human lives, to the environment or to expensive equipment, significantly increased the need for dependable systems, able to detect, tolerate and eventually correct faults. The verification and validation of such systems is frequently performed via fault injection, using various forms and techniques. However, as electronic devices get smaller and more complex, controllability and observability issues, and sometimes real time constraints, make it harder to apply most conventional fault injection techniques. This paper proposes a fault injection environment and a scalable methodology to assist the execution of real-time fault injection campaigns, providing enhanced performance and capabilities. Our proposed solutions are based on the use of common and customized on-chip debug (OCD) mechanisms, present in many modern electronic devices, with the main objective of enabling the insertion of faults in microprocessor memory elements with minimum delay and intrusiveness. Different configurations were implemented starting from basic Components Off-The-Shelf (COTS) microprocessors, equipped with real-time OCD infrastructures, to improved solutions based on modified interfaces, and dedicated OCD circuitry that enhance fault injection capabilities and performance. All methodologies and configurations were evaluated and compared concerning performance gain and silicon overhead.

Embedded System Level Self-Test for Mixed-Signal IO Verification

This article presents an embedded system level self-test implementation for verification of a peripheral and its connectivity to the system. The self-test enables to perform a test for verifying the IO connectivity from inside the system. The proposed on-chip-testing scheme exploits IC level CMOS testability structures. The IC level DFT structure is verified. The scheme is confirmed by minor silicon overhead. The system level methodology is applied for a peripheral test. The methodology is evaluated by analyzing the response signal and by making a histogram data analysis. The applicability of the methodology is evaluated by comparing it to the existing methods. The article will define the approach, will list the main benefits of this methodology, analyze the laboratory test results and show the changes that need to be implemented in a mixed-signal IC in order to achieve this system level testability.

A fault-tolerant message passing algorithm and its hardware implementation

A message passing algorithm for processor arrays that can tolerate any number of faulty blocks, which form any shape, is presented. Each message is delivered to its destination, provided that the destination processor is not surrounded by faults. In this case the message is returned to its source processor. Only local knowledge of faults is demanded. The hardware implementation of this algorithm leads to a message passing coprocessor which is allocated at each processor of the array. No need for high silicon overhead is required for the implementation of the message passing coprocessor. This coprocessor executes only the fault tolerant message passing algorithm presented here. The usage of the proposed coprocessor improves the general processing efficiency, as well as, the performance reliability under faulty conditions.

SMT layout overhead and scalability

Simultaneous Multi-Threading (SMT) is a hardware technique that increases processor throughput by issuing instructions simultaneously from multiple threads. However, while SMT can be added to an existing microarchitecture with relatively low overhead, this additional chip area could be used for other resources such as more functional units, larger caches, or better branch predictors. How large is the SMT overhead and at what point does SMT no longer pay off for maximum throughput compared to adding other architecture features? This paper evaluates the silicon overhead of SMT by performing a transistor/interconnect-level analysis of the layout. We discuss microarchitecture issues that impact SMT implementations and show how the Instruction Set Architecture (ISA) and microarchitecture can have a large effect on the SMT overhead and performance. Results show that SMT yields large performance gains with small to moderate area overhead.

Built-in self-test: Early developments and future trends

This paper describes the early developments of Built-In Self-Test in retrospect and gives an outlook on future trends of this technique. The steps for eliminating the initial shortcomings, like silicon overhead, aliasing, and inefficient test patterns, which hindered the quick acceptance of self-test are discussed. New test challenges which are likely to be induced by the rapid progress in semiconductor technology are described. It is outlined how these problems can be solved by self-test.

Compact BIC sensor for testing Iddq of CMOS circuits

A compact built-in current sensor based on a slightly modified latch comparator is presented, which allows fast detection and memorising of excessively high quiescent current without the need for a voltage reference. Response time, virtual ground distortion and silicon overhead are analysed in order to evaluate the sensor performance.

A new built-in self-repair approach to VLSI memory yield enhancement by using neural-type circuits

It is shown how to represent the objective function of the memory repair problem as a neural-network energy function, and how to exploit the neural network's convergence property for deriving optimal repair solutions. Two algorithms have been developed using a neural network, and their performances are compared with that of the repair most (RM) algorithm. For randomly generated defect patterns, a proposed algorithm with a hill-climbing capability successfully repaired memory arrays in 98% cases, as opposed to RMs 20% cases. It is demonstrated how, by using very small silicon overhead, one can implement this algorithm in hardware within a VLSI chip for built in self repair (BISR) of memory arrays. The proposed auto-repair approach is shown to improve the VLSI chip yield by a significant factor, and it can also improve the life span of the chip by automatically restructuring its memory arrays in the event of sporadic cell failures during the field use.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Realistic built-in self-test for static RAMs

The authors present the specification and design of a self-test mechanism for static random-access memories (RAMs). The test algorithm provides excellent fault detection, and its structure is independent of address and data scrambling. The self-test machine generates data backgrounds on chip and is therefore suitable for both bit-oriented and word-oriented SRAMs. It is also suitable for both embedded SRAMs and stand-alone SRAMs, and adapts to boundary-scan environment. Because of the regular and symmetric structure of the test algorithm, the silicon overhead is only 3% for a 16 K synchronous SRAM.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Reconfiguration of hexagonal arrays by diagonal deletion

This paper describes various algorithms for dynamic reconfiguration of VLSI hexagonal arrays. These algorithms are applicable to arrays in which reconfiguration requires logical deletion of the diagonal front of computation. Initially it is proven that the intuitive, but rather naive approach of diagonal deletion is not correct, because it does guarantee the generation of the correct dimensions in the target array. A new approach based on geometrical considerations is proposed. Theorems that preserve the dimensions of the desired target array, are presented. Two reconfiguration algorithms are presented. These algorithms have linear time-complexity with respect to the dimensions of the array. The innovative features of this approach are the dependence of reconfiguration on the dimensions of the array to be reconfigured and a better exploitation of redundancy for run-time reconfiguration. Simple switching circuits are described. It is proved that silicon overhead consists of four two-by-two Banyan switches per cell. Illustrative examples are presented.