Silicon-on-sapphire Substrates Research Articles

Integration of epitaxial La2/3Sr1/3MnO3 thin films on silicon-on-sapphire substrate for MEMS applications

We report the integration of high-quality epitaxial La2/3Sr1/3MnO3 (LSMO) thin films onto SrTiO3 buffered Silicon-on-Sapphire (SOS) substrates by combining state-of-the-art thin film growth techniques such as molecular beam epitaxy and pulsed laser deposition. Detailed structural, magnetic and electrical characterizations of the LSMO/STO/SOS heterostructures show that the LSMO film properties are competitive with those directly grown on oxide substrates. X-ray magnetic circular dichroism measurements on Mn L2,3 edges show strong dichroic signal at room temperature, and angular-dependent in-plane magnetic properties by magneto-optical Kerr magnetometry reveal isotropic magnetic anisotropy. Suspended micro-bridges were thus finally fabricated by silicon micromachining, thus demonstrating the potential use of integrating LSMO magnetic layer on industrially compatible SOS substrates for the development of applicative MEMS devices.

Improvement in Self-Heating Characteristic by Utilizing Sapphire Substrate in Omega-Gate-Shaped Nanowire Field Effect Transistor for Wearable, Military, and Aerospace Application

In this study, we propose an omega-shaped-gate nanowire field effect transistor (ONWFET) with a silicon-on-sapphire (SOS) substrate. In order to investigate improvements in the self-heating characteristic with the use of a SOS substrate, the lattice temperature is examined using a Synopsys Sentaurus 3D Technology computer-aided design (TCAD) simulator with the results compared to those with a silicon-on-insulator (SOI) substrate. To validate the proposed structure with the SOS substrate, the locations of hot spots and heat dissipation paths (heat sinks) depending on the substrate materials are also analyzed. The electrical characteristics, specifically the on-current (Ion), off-current (Ioff), and subthreshold swing (SS), were investigated as well. Hence, it is demonstrated here that incorporating a SOS substrate can improve both the self-heating characteristic and the SS at the same time. Therefore, enhanced logic devices are feasible if using an ONWFET with a SOS substrate. Examples include wearable devices and military and future aerospace applications achieved by the radiation-resistant material Al₂O₃ that has high thermal conductivity.

Improvement of Crystalline Quality in GaAs Layer Grown on Thermal Cyclic Annealed SOS

High quality GaAs layer grown on silicon-on-sapphire (SOS) have been successfully achieved by thermal cyclic annealing (TCA) procedure using the two reactor MOCVD system after Si film deposition. The quality of silicon film measured by X-ray diffraction showed 50% narrowing of full width at half maximum intensity (FWHM) after TCA process. A spherical sapphire substrate was used to investigate substrate Offset angle dependence on crystalline quality of the GaAs layer. By applying TCA for SOS substrate before GaAs layer growth, extra smooth surface whose roughness of less than ±30nm could obtained within a wide area of spherical SOS surface. At the smooth region, clear Franz-Keldysh oscillations (FKOs) were observed by photoreflectance (PR) spectroscopy. It also indicated that the cystalline quality of GaAs layer grown on TCA treated SOS was extremly high.

A monolithic isolation amplifier in silicon-on-insulator CMOS: Testing and applications

In this paper, the design and test results of a 4-channel digital isolation amplifier are presented, along with results of a prototype power converter circuit using the amplifier for voltage feedback regulation. The amplifier uses a capacitive coupling technique to transfer digital signals from input to output while preserving galvanic isolation between the two. The isolation amplifier was fabricated in a 0.5 ?m Silicon-on-Sapphire (SOS) technology and uses the isolation properties of the SOS substrate to achieve more than 800 V isolation between input and output grounds. Each of the four channels can operate in excess of 100 Mbps using a differential transmission scheme to reject ground bounce transients up to 1 V/?s. The input circuit can be powered from an on-chip charge-pump to permit single supply operation. The device can be used in a wide variety of applications that require passing signals across an isolation barrier: power supplies, remote sensing, and medical and industrial applications.

Backside-Illuminated Lateral PIN Photodiode for CMOS Image Sensor on SOS Substrate

In this paper, we propose a method to design charge-sensing elements for CMOS image sensor pixels on a silicon-on-sapphire (SOS) substrate. To address the low quantum efficiency problem due to very thin active film used, a backside illuminated lateral PIN photodiode on an SOS substrate is proposed and developed. It has the advantages of higher photo response with a PIN structure and improved optical transmission with a backside illumination through a transparent sapphire substrate. An active pixel sensor (APS) based on the PIN and backside illumination has been implemented in a commercially available SOS CMOS process. Acceptable sensitivity in optical conversion from the APS can be achieved, even with the ultrathin silicon film. The APS is demonstrated to function at 1.2 V, giving a dynamic range of 51 dB.

A 200 V silicon-on-sapphire LDMOS structure with a step oxide extended field plate

Fabrication of power integrated circuits on silicon-on-sapphire (SOS) substrates has rarely been considered before. Hence, there is a lack of research in lateral power devices integrated on SOS. Self-heating effects in existing silicon-on-insulator (SOI) lateral power devices degrade the device performance and their reliability. Use of SOS substrates could alleviate these problems though they would require a different approach in lateral power device engineering. This paper purposes a new power SOS LDMOS structure with reduced transient self-heating effects and enhanced current capability compared to the conventional SOI counterpart. The proposed lateral power structure integrated on SOS substrates is analyzed by electro-thermal simulations. The field plate is enlarged (extended field plate (EFP)) along the drift region, reaching the drain region. The EFP includes an oxide step which improves the “on-state resistance–breakdown voltage” trade-off ( R ONxS– V br).

4- and 13-GHz tuned amplifiers implemented in a 0.1-μm CMOS technology on SOI, SOS, and bulk substrates

Four- and 13-GHz tuned amplifiers have been implemented in a partially scaled 0.1-1 /spl mu/m CMOS technology on bulk, silicon-on-insulator (SOI), and silicon-on-sapphire (SOS) substrates. The 4-GHz bulk, SOI, and SOS amplifiers exhibit forward gains of 14, 11, and 12.5 dB and F/sub min/'s of 4.5 (bulk) and 3.5 db (SOS). The 13-GHz SOS and SOI amplifiers exhibit gains of 15 and 5.3 dB and F/sub unn/'s of 4.9 and 7.8 dB. The 4-GHz bulk amplifier has the highest resonant frequency among reported bulk CMOS amplifiers, while the 13-GHz SOS and SOI amplifiers are the first in a CMOS technology to have tuned frequencies greater than 10 GHz. These and other measurement results suggest that it may be possible to implement 20-GHz tuned amplifiers in a fully scaled 0.1-1 /spl mu/m CMOS process.

Nickel silicide thermal stability on polycrystalline and single crystalline silicon

The thermal stability of NiSi on polycrystalline silicon (poly-Si) or single crystalline silicon on sapphire (SOS) substrates has been investigated with scanning electron microscopy, transmission electron microscopy, and in-situ resistance measurements. For NiSi on poly-Si, silicide enhanced grain growth occurs in the poly-Si. The grain growth first occurs from the NiSi/poly-Si interface with poly-Si grains growing into the silicide, resulting in alternating grains of poly-Si and NiSi on the top surface. With further annealing, grain growth also occurs in the bottom layer of the poly-Si, with NiSi moving to the bottom interface and consuming the small poly-Si grains, resulting in an inverted structure. Agglomeration of NiSi is observed for NiSi on SOS substrates after high temperature annealing. The activation energies for inversion and agglomeration are similar, (3.0 ± 0.2 and 2.9 ± 0.2 eV, respectively) suggesting that the same mechanism is controlling both processes. The activation energy may correspond to that for adding a Si atom onto a growing Si grain, as suggested by L.H. Allen, K.N. Tu, L.C. Feldman, and J.W. Mayer, Phys. Rev. B, 41 (1990) 8213.

High- Tc edge-geometry SNS weak links on silicon-on-sapphire substrates

High-quality superconductor/normal-metal/superconductor (SNS) edge-geometry weak links have been produced on silicon-on-sapphire (SOS) substrates using a new SrTiO 3/“seed-layer”/cubic-zirconia (YSZ) buffer system. The seed layer is a thin YBa 2Cu 3O 7- x (YBCO) or PrBa 2Cu 3O 7- x (PBCO) film, which provides a template for growth of the SrTiO 3. This multilayer buffer system eliminates problems with series grain-boundary weak links seen in edge junctions on single YSZ buffer layers on SOS, while the use of moderate-dielectric-constant SOS substrates should benefit high-frequency applications and enable integration with silicon circuitry. SNS weak links fabricated on SOS with PBCO and Co doped YBCO normal-metal layers exhibit current-voltage characteristics qualitatively consistent with the resistively shunted junction model, with modulating AC Josephson steps and operation to temperatures above 77 K. These are the first reported epitaxial edge-geometry SNS devices on SOS substrates.

Chemical vapor deposition of β-SiC on silicon-on-sapphire and silicon-on-insulator substrates

Cubic silicon carbide (β-SiC) films have been grown epitaxially on silicon-on-sapphire (SOS) substrates by chemical vapor deposition. A fresh layer of silicon is first deposited in situ on the SOS substrate at approximately 1050°C. The silicon layer is then carbonized while being heated to 1360°C. The β-SiC layer is grown at 1360°C using silane and propane as sources. β-SiC films can also be grown directly on the SOS substrate without utilizing a fresh silicon layer. Deposition of β-SiC films on silicon-on-insulator (SOI) substrates has also been accomplished with slight modification of the growth parameters described above.The β-SiC films have been characterized by IR reflectance spectroscopy, optical microscopy and electron microscopy. Typical films are 7 μm thick and have a specular surface with some physical features. Electrical transport properties as determined by the Van der Pauw Hall method show the β-SiC films to be p-type while those grown on SOI were n-type. X-ray rocking curve measurements were obtained to determine the crystalline quality of the films. In addition, preliminary optical characterization of the films has been performed.

Epitaxial growth of β-SiC on silicon-on-sapphire substrates by chemical vapor deposition

Cubic (β) silicon carbide films have been grown epitaxially on silicon-on-sapphire (SOS) substrates by chemical vapor deposition. The β-SiC films were grown between 1340–1370 °C on SOS substrates which have a layer of silicon deposited in situ or were grown directly on the as-is SOS substrate. In both cases, the silicon surface was carbonized prior to growth of the β-SiC epilayer. With a growth rate of ∼3.5 μm/h, 7 μm β-SiC films have been obtained. The films have been characterized by infrared reflectance spectroscopy, optical and scanning electron microscopy. Specular films are obtained which have growth columns and pits. Electrical transport properties of the films were measured by the Van der Pauw–Hall method. The films are p type with carrier concentrations between 1×1018 and 2×1018 cm−3 and Hall mobilities of approximately 30 cm2/V s.

I n s i t u laser deposition of Y1Ba2Cu3O7−x high T c superconducting thin films with SrTiO3 underlayers

Thin films of Y1Ba2Cu3O7−x (YBCO) with and without underlayers of SrTiO3 (STO) were deposited via pulsed laser deposition onto substrates of sapphire and silicon-on-sapphire (SOS) in a single vacuum step. The YBCO films with STO underlayers displayed better superconducting transitions than the YBCO films without underlayers, with zero-resistance temperatures of 86.5 and 75 K for films with underlayers on sapphire and SOS substrates, respectively. X-ray diffraction and secondary-ion mass spectroscopy have been used to explore the role played by the STO underlayer in improving film quality.

Laser-assisted direct writing of strain sensitive silicon resistors

The laser-induced deposition of doped silicon lines from mixtures of silane and diborane using an argon-ion laser is reported. The piezoresistive properties of the lines deposited on different substrate materials, such as sapphire and silicon-on-sapphire (SOS), are investigated because of their potential use as pressure sensor elements. The lines deposited on sapphire, using a gas mixture that contains 1% diborane in silane, exhibit polycrystalline characteristics with gauge factors less than about 20. The lines deposited on SOS substrates, on the other hand, show anisotropic characteristics in their piezoresistivity properties. The maximum gauge factor in this case is of the order of 44. Still higher gauge factors up to 77 are obtained using a gas mixture with 0.1% diborane in silane. The use of this technology for pressure sensor development is being studied by the construction and testing of diaphragm-type pressure sensor prototypes.

Subthreshold behaviour of silicon MESFETs on SOS and bulk silicon substrates

The subthreshold characteristics of silicon MESFETs manufactured using both bulk silicon and silicon-on-sapphire (SOS) technology, have been studied. n- and p-type devices have been investigated and their characteristics are presented here. The results show that the subthreshold behaviour for bulk devices in fully comparable with that of MESFETs, while the SOS devices show a somewhat lower value of subthreshold swing. A comparison between calculated and experimental behaviour is presented which yields information about the influence of the geometry and processing parameters of the subthreshold behaviour. It is proposed that the saturation subthreshold current for bulk transistors can be decreased by a proper design. An improvement for SOS devices, however, requires improved substrate material.

Growth and Characterization of Heteroepitaxial GaAs on Semiconductor-on-Insulator and Insulating Substrates

AbstractA systematic study pertaining to the molecular beam epitaxial growth and charac- terization of GaAs films on various crystallographic orientations of sapphire is presented. For integration with silicon circuitry, heteroepitaxial GaAs layers have also been grown on commercially-available chemical vapor deposited silicon-on-sapphire (SOS) and SOS substrates that have been upgraded by the double solid-phase epitaxy process.

Microwave MESFET's fabricated in GaAs layers grown on SOS Substrates

Device-quality GaAs layers have been grown on silicon-on-sapphire (SOS) substrates by molecular beam epitaxy (MBE). Microwave MESFET's (gate length of ~0.8 µm) with transconductance of 140 mS/ mm, f_{\max} = 20 GHz, and f_{T} = 8.3 GHz have been fabricated in these layers.

Selective reactive ion etching of silicon dioxide : J. S. Chang. Solid St. Technol. 214 (April 1984)

Cubic silicon carbide (β-SiC) films have been grown epitaxially on silicon-on-sapphire (SOS) substrates by chemical vapor deposition. A fresh layer of silicon is first deposited in situ on the SOS substrate at approximately 1050°C. The silicon layer is then carbonized while being heated to 1360°C. The β-SiC layer is grown at 1360°C using silane and propane as sources. β-SiC films can also be grown directly on the SOS substrate without utilizing a fresh silicon layer. Deposition of β-SiC films on silicon-on-insulator (SOI) substrates has also been accomplished with slight modification of the growth parameters described above.The β-SiC films have been characterized by IR reflectance spectroscopy, optical microscopy and electron microscopy. Typical films are 7 μm thick and have a specular surface with some physical features. Electrical transport properties as determined by the Van der Pauw Hall method show the β-SiC films to be p-type while those grown on SOI were n-type. X-ray rocking curve measurements were obtained to determine the crystalline quality of the films. In addition, preliminary optical characterization of the films has been performed.