Silicon-on-insulator Nanowire Research Articles

Simulation of Quantum Current Oscillations in Trigate SOI MOSFETs

In this paper, we simulate quantum transport in trigate silicon-on-insulator (SOI) nanowire field-effect transistors using 3-D numerical simulations. The formation of 1-D subbands in SOI nanowire, which results in the oscillation of the current and transconductance characteristic at low temperatures, has been studied in detail. These oscillations correspond to the filling of energy subbands by electrons as the gate voltage is increased, thereby enabling the experimental evaluation of the subband energy spacing in nanowire structures (subband spectroscopy).

Theoretical investigation of nanowaveguide‐based optical coupler using mode expansion transfer matrix

AbstractWe report a mode expansion transfer matrix method to describe the nanowaveguide‐based strongly coupling waveguide directional couplers, including slab nanowaveguide coupler, silicon‐on‐insulator (SOI) nanowires coupler, and silica nanofibers coupler. We propose a general mode expansion description of coupler without the assumption of weakly guiding. For the slab nanowaveguide case, all the coefficients inside those matrices could be identified theoretically using mode expansion method. The analytical results of coupler show excellent agreement with the simulation results obtained by the finite‐difference time‐domain method. For the nanofiber coupler, with the mode profiles obtained numerically using finite element method, similar matrix equation could be used for the guideline of nanofiber coupler design, which is the key issue of coupler‐based nanofiber devices and SOI nanowires devices. © 2010 Wiley Periodicals, Inc. Microwave Opt Technol Lett 52: 1123–1129, 2010; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.25093

Silicon nanowire transistors for electron biosensors

A method of nanostructuring of silicon-on-insulator (SOI) layers on the basis of gas etching in XeF2 or SF6:CFCl3 is developed for the purpose of obtaining SOI nanowire structures. SOI nanowire transistors (SOI NWTs) with free channels, used as sensors in electron detectors, are fabricated and tested. The results of experiments show that the method used to fabricate nanowires requires no high-temperature operations for elimination of defects after nanostructuring of SOI layers. The sensitivity of SOI NWTs to test molecules of bovine serum albumin is 10−15 mole/liter, which is one of the best results for nanowire biosensors.

Comparative Study of Losses in Ultrasharp Silicon-on-Insulator Nanowire Bends

Ultrasharp silicon-on-insulator (SOI) nanowire bends (with a bending radius of <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">R</i> < 2 mu m) are analyzed numerically. It is shown that the calculated bending losses for ultrasharp bends are overestimated when using a modal analysis method based on finite-difference method. In this case, reliable estimation of the bending loss can be made with a 3-D finite-difference time-domain (3-D-FDTD) method. By using 3-D-FDTD simulation, the losses in SOI nanowire bends with different structures and parameters are studied. By increasing the core width or height of the waveguide, one can reduce the bending loss at longer wavelengths for TE mode while the bending performance at shorter wavelengths degrades due to the multimode effect. Increasing the core height is much more effective to reduce the bending loss of TM mode than increasing core width. The relationship between the intrinsic <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Q</i> -factor of a microring resonator and the bending radius is also obtained.

Silicon-on-Insulator-Based Radio Frequency Single-Electron Transistors Operating at Temperatures above 4.2 K

A radio frequency single-electron transistor (RF-SET) based on a silicon-on-insulator (SOI) substrate is demonstrated to operate successfully at temperatures above 4.2 K. The SOI SET was fabricated by inducing lateral constrictions in doped SOI nanowires. The device structure was optimized to overcome the inherent drawback of high resistance with the SOI SETs. We performed temperature variation measurements after five thermal cyclings of the same sample to 4.2 K and found that the single-dot device transport characteristics are highly stable. The charge sensitivity was measured to be 36 microe(rms) Hz(-1/2) at 4.2 K, and the RF-SET operation was demonstrated up to 12.5 K for the first time. This work is an important prerequisite to realizing operation of RF-SETs at noncryogenic temperatures.

Numerical analysis of silicon-on-insulator ridge nanowires by using a full-vectorial finite-difference method mode solver

The characteristics of silicon-on-insulator (SOI) ridge waveguides are analyzed by using a cylindrical full-vectorial finite-difference method mode solver with a perfectly-matched layer treatment. First, the single-mode condition for an SOI ridge nanowire with different Si core thicknesses is obtained. The obtained single-mode condition is different from that for the conventional micrometrical SOI ridge waveguides with a large cross section. By adjusting the cross section (the core width and the etching depth), one can have a nonbirefringent SOI ridge nanowire. The analysis on the bending loss of SOI ridge nanowires shows that one can have a relatively small bending radius even with a shallow etching (i.e., a small ratio γ between the etching depth and the total thickness). For example, even when one chooses a small ratio γ=0.4, one still has a low bending loss with a small bending radius of 15 μm for an SOI nanowire with a thin core hco=250 nm, which is very different from a conventional large SOI ridge waveguide.

Conduction in ultra-thin SOI nanowires prototyped by FIB milling

This work describes a simple yet fast fabrication method to prototype silicon-on-insulator nanowires (SOINW) by using FIB milling and sacrificial oxidation on SOI substrate. Al-gated silicon wires with 8 nm diameter and 50–200 nm length are successfully demonstrated. The Si-wires are heavily implanted with phosphorus in between two oxidation steps, resulting in a film structure in which the hopping conduction mode occurs in the electron accumulation regime. Conduction oscillations are observed in 8 nm diameter Si-wires at room temperature, in contrast with large geometry samples where no oscillations are visible even at low temperature and where the conduction appears as being temperature activated.

Fabrication of single-electron tunneling transistors with an electrically formed Coulomb island in a silicon-on-insulator nanowire

For the purpose of controllable characteristics, silicon single-electron tunneling transistors with an electrically formed Coulomb island are proposed and fabricated on the basis of the sidewall process technique. The fabricated devices are based on a silicon-on-insulator (SOI) metal–oxide–semiconductor (MOS) field effect transistor with the depletion gate. The key fabrication technique consists of two sidewall process techniques. One is the patterning of a uniform SOI nanowire, and the other is the formation of n-doped polysilicon sidewall depletion gates. While the width of a Coulomb island is determined by the width of a SOI nanowire, its length is defined by the separation between two sidewall depletion gates which are formed by a conventional lithographic process combined with the second sidewall process. These sidewall techniques combine the conventional lithography and process technology, and guarantee the compatibility with complementary MOS process technology. Moreover, critical dimension depends not on the lithographical limit but on the controllability of chemical vapor deposition and reactive-ion etching. Very uniform weakly p-doped SOI nanowire defined by the sidewall technique effectively suppresses unintentional tunnel junctions formed by the fluctuation of the geometry or dopant in SOI nanowire, and the Coulomb island size dependence of the device characteristics confirms the good controllability. A voltage gain larger than one and the controllability of Coulomb oscillation peak position are also successfully demonstrated, which are essential conditions for the integration of a single-electron tunneling transistor circuit. Further miniaturization and optimization of the proposed device will make room temperature designable single-electron tunneling transistors possible in the foreseeable future.