Silicon Neurons Research Articles

Subthreshold CMOS Array for Generating a Gaussian Distribution of Currents

This brief presents a subthreshold CMOS array whose spatial distribution of output currents approximates a Gaussian, and the distribution has an independently controllable mean and standard deviation. This Gaussian distribution naturally results from the transistor physics of subthreshold CMOS equations and the symmetry imposed in the network. The usefulness of the circuit array is demonstrated in a system-level example by using the currents to drive integrate-and-fire silicon neurons in which the neuronal input current and the resulting interspike interval are inversely related. The circuit and silicon neuron arrays were fabricated on the same integrated-circuit chip using the MOSIS AMI 0.5-mum process, and testing yielded experimental results that matched well with theoretical analysis

Two-Dimensional Variation of Bursting Properties in a Silicon-Neuron Half-Center Oscillator

We are developing hardware models of central pattern generators (CPGs) to enhance neural prostheses, create biologically based controllers for autonomous machines, and to better understand how biology creates stable and robust movements. Previously, we designed and implemented an analog integrated circuit model of a neuron with Hodgkin-Huxley like dynamics, the silicon neuron. In this work, we use silicon neurons to implement a half-center oscillator and show that the underlying dynamics of this CPG produce bursting behaviors that are well matched to the biological counterpart on which our model is based. In addition, we demonstrate the robustness of the bursting behavior by systematically varying two parameters in each silicon neuron and mapping the corresponding effects on the bursting.

An asynchronous architecture for modeling intersegmental neural communication

This paper presents an asynchronous VLSI architecture for modeling the oscillatory patterns seen in segmented biological systems. The architecture emulates the intersegmental synaptic connectivity observed in these biological systems. The communications network uses address-event representation (AER), a common neuromorphic protocol for data transmission. The asynchronous circuits are synthesized using communicating hardware processes (CHP) procedures. The architecture is scalable, supports multichip communication, and operates independent of the type of silicon neuron (spiking or burst envelopes). A 16-segment prototype system was developed, tested, and implemented; data from this system are presented.

A VLSI Array of Low-Power Spiking Neurons and Bistable Synapses With Spike-Timing Dependent Plasticity

We present a mixed-mode analog/digital VLSI device comprising an array of leaky integrate-and-fire (I&F) neurons, adaptive synapses with spike-timing dependent plasticity, and an asynchronous event based communication infrastructure that allows the user to (re)configure networks of spiking neurons with arbitrary topologies. The asynchronous communication protocol used by the silicon neurons to transmit spikes (events) off-chip and the silicon synapses to receive spikes from the outside is based on the "address-event representation" (AER). We describe the analog circuits designed to implement the silicon neurons and synapses and present experimental data showing the neuron's response properties and the synapses characteristics, in response to AER input spike trains. Our results indicate that these circuits can be used in massively parallel VLSI networks of I&F neurons to simulate real-time complex spike-based learning algorithms.

Restoring lost cognitive function

A prosthetic device that functions in a biomimetic manner to replace information transmission between cortical brain regions is considered. In such a prosthesis, damaged CNS neurons is replaced with a biomimetic system comprised of silicon neurons. The replacement silicon neurons would have functional properties specific to those of the damaged neurons and would both receive as inputs and send as outputs electrical activity to regions of the brain with which the damaged region previously communicated. Thus, the class of prosthesis proposed is one that would replace the computational function of the damaged brain and restore the transmission of that computational result to other regions of the nervous system.

A bio-physically inspired silicon neuron

The physical principles governing ion flow in biological neurons share interesting similarities to electron flow through the channels of MOSFET transistors. Here, is described a circuit which exploits the similarities better than previous approaches to build an elegant circuit with electrical properties similar to real biological neurons. A two-channel model is discussed including sodium (Na/sup +/) and potassium (K/sup +/). The Na/sup +/ channel uses four transistors and two capacitors. The K/sup +/ channel uses two transistors and one capacitor. One more capacitor simulates the neuron membrane capacitance yielding a total circuit of four capacitors and six transistors. This circuit operates in real-time, is fabricated on standard CMOS processes, runs in subthreshold, and has a power supply similar to that of real biology. Voltage and current responses of this circuit correspond well with biology in terms of shape, magnitude, and time.

Bifurcation of synchronous oscillations into torus in a system of two reciprocally inhibitory silicon neurons: Experimental observation and modeling

Oscillatory activity in the central nervous system is associated with various functions, like motor control, memory formation, binding, and attention. Quasiperiodic oscillations are rarely discussed in the neurophysiological literature yet they may play a role in the nervous system both during normal function and disease. Here we use a physical system and a model to explore scenarios for how quasiperiodic oscillations might arise in neuronal networks. An oscillatory system of two mutually inhibitory neuronal units is a ubiquitous network module found in nervous systems and is called a half-center oscillator. Previously we created a half-center oscillator of two identical oscillatory silicon (analog Very Large Scale Integration) neurons and developed a mathematical model describing its dynamics. In the mathematical model, we have shown that an in-phase limit cycle becomes unstable through a subcritical torus bifurcation. However, the existence of this torus bifurcation in experimental silicon two-neuron system was not rigorously demonstrated or investigated. Here we demonstrate the torus predicted by the model for the silicon implementation of a half-center oscillator using complex time series analysis, including bifurcation diagrams, mapping techniques, correlation functions, amplitude spectra, and correlation dimensions, and we investigate how the properties of the quasiperiodic oscillations depend on the strengths of coupling between the silicon neurons. The potential advantages and disadvantages of quasiperiodic oscillations (torus) for biological neural systems and artificial neural networks are discussed.

Synchrony detection and amplification by silicon neurons with STDP synapses.

Spike-timing dependent synaptic plasticity (STDP) is a form of plasticity driven by precise spike-timing differences between presynaptic and postsynaptic spikes. Thus, the learning rules underlying STDP are suitable for learning neuronal temporal phenomena such as spike-timing synchrony. It is well known that weight-independent STDP creates unstable learning processes resulting in balanced bimodal weight distributions. In this paper, we present a neuromorphic analog very large scale integration (VLSI) circuit that contains a feedforward network of silicon neurons with STDP synapses. The learning rule implemented can be tuned to have a moderate level of weight dependence. This helps stabilise the learning process and still generates binary weight distributions. From on-chip learning experiments we show that the chip can detect and amplify hierarchical spike-timing synchrony structures embedded in noisy spike trains. The weight distributions of the network emerging from learning are bimodal.

Coupling an aVLSI neuromorphic vision chip to a neurotrophic model of synaptic plasticity: the development of topography.

We couple a previously studied, biologically inspired neurotrophic model of activity-dependent competitive synaptic plasticity and neuronal development to a neuromorphic retina chip. Using this system, we examine the development and refinement of a topographic mapping between an array of afferent neurons (the retinal ganglion cells) and an array of target neurons. We find that the plasticity model can indeed drive topographic refinement in the presence of afferent activity patterns generated by a real-world device. We examine the resilience of the developing system to the presence of high levels of noise by adjusting the spontaneous firing rate of the silicon neurons.

Control of bursting properties in a silicon neuron CPG

We have developed a silicon neuron based on a heart interneuron of the leech. We created a half-center oscillator composed of two silicon neurons connected via inhibitory synapses implemented through dynamic clamp. We investigated the effects of symmetrical variations of maximal conductances on bursting behavior. Burst period, average burst spike frequency, and duty cycle were chosen as major characteristics of the bursting waveform. Burst period and spike frequency showed similar dependencies on the varied parameters in both neurons; duty cycles of the two neurons, however, diverged when the parameters were varied, reflecting mismatch in parameters between chips.

Neuromorphic hardware databases for exploring structure-function relationships in the brain.

Neuromorphic hardware is the term used to describe full custom-designed integrated circuits, or silicon 'chips', that are the product of neuromorphic engineering--a methodology for the synthesis of biologically inspired elements and systems, such as individual neurons, retinae, cochleas, oculomotor systems and central pattern generators. We focus on the implementation of neurons and networks of neurons, designed to illuminate structure-function relationships. Neuromorphic hardware can be constructed with either digital or analogue circuitry or with mixed-signal circuitry--a hybrid of the two. Currently, most examples of this type of hardware are constructed using analogue circuits, in complementary metal-oxide-semiconductor technology. The correspondence between these circuits and neurons, or networks of neurons, can exist at a number of levels. At the lowest level, this correspondence is between membrane ion channels and field-effect transistors. At higher levels, the correspondence is between whole conductances and firing behaviour, and filters and amplifiers, devices found in conventional integrated circuit design. Similarly, neuromorphic engineers can choose to design Hodgkin-Huxley model neurons, or reduced models, such as integrate-and-fire neurons. In addition to the choice of level, there is also choice within the design technique itself; for example, resistive and capacitive properties of the neuronal membrane can be constructed with extrinsic devices, or using the intrinsic properties of the materials from which the transistors themselves are composed. So, silicon neurons can be built, with dendritic, somatic and axonal structures, and endowed with ionic, synaptic and morphological properties. Examples of the structure-function relationships already explored using neuromorphic hardware include correlation detection and direction selectivity. Establishing a database for this hardware is valuable for two reasons: first, independently of neuroscientific motivations, the field of neuromorphic engineering would benefit greatly from a resource in which circuit designs could be stored in a form appropriate for reuse and re-fabrication. Analogue designers would benefit particularly from such a database, as there are no equivalents to the algorithmic design methods available to designers of digital circuits. Second, and more importantly for the purpose of this theme issue, is the possibility of a database of silicon neuron designs replicating specific neuronal types and morphologies. In the future, it may be possible to use an automated process to translate morphometric data directly into circuit design compatible formats. The question that needs to be addressed is: what could a neuromorphic hardware database contribute to the wider neuroscientific community that a conventional database could not? One answer is that neuromorphic hardware is expected to provide analogue sensory-motor systems for interfacing the computational power of symbolic, digital systems with the external, analogue environment. It is also expected to contribute to ongoing work in neural-silicon interfaces and prosthetics. Finally, there is a possibility that the use of evolving circuits, using reconfigurable hardware and genetic algorithms, will create an explosion in the number of designs available to the neuroscience community. All this creates the need for a database to be established, and it would be advantageous to set about this while the field is relatively young. This paper outlines a framework for the construction of a neuromorphic hardware database, for use in the biological exploration of structure-function relationships.

Space-rate coding in an adaptive silicon neuron

Neurophysiology is largely the study of spike rates of single neurons, under controlled conditions, with the hope that these results reflect how populations of neurons compute. However, the population response differs radically from the single-neuron response if the membrane voltage's rate of change drops dramatically when it is close to the spike-firing threshold. By delaying spiking, this slew-rate adaptation has been shown to regulate spike rate and prolong synaptic integration at the single-neuron level. We show here that it sharpens sensitivity and shortens latency at the population level. Thus, slew-rate adaptation enables neurons to process information faster than their interspike interval by using space-rate coding, instead of time-rate coding. This study also suggests how neural populations can modulate their gain and synchrony by regulating active conductances. Our results are extrapolated from experiments and analysis performed on a single silicon neuron, with Ca- and voltage-dependent potassium-channel analogs.

Equivalence transformations for dendritic Y-junctions: a new definition of dendritic sub-unit

A sequence of equivalence transformations is used to represent the mathematical model of a simply branched neuron with non-homogeneous membrane properties and non-uniform geometry by an entirely equivalent model of an unbranched structure. The analysis indicates how neuronal morphology, in combination with its biophysical properties, shapes neuronal output in response to current input. The equivalence transformations described here reveal the types of operations that are likely to feature in the analysis of complex multi-branched structures, neuronal or otherwise. These transformations provide a new definition of dendritic sub-unit and a basis of a mechanism for characterising local and non-local signal processing within dendritic structures. It is anticipated that the capacity to transform biological neurons into an equivalent unbranched structure will make an important contribution to the understanding of the functional role of neuron geometry as well as to the construction of silicon neurons with realistic biological properties.

Forward- and backpropagation in a silicon dendrite

We have developed an analog very-large-scale integrated (aVLSI) electronic circuit that emulates a compartmental model of a neuronal dendrite. The horizontal conductances of the compartmental model are implemented as a switched capacitor network. The transmembrane conductances are implemented as transconductance amplifiers. The electrotonic properties of our silicon cable are qualitatively similar to those of the ideal passive cable that is commonly used to model mathematically the electrotonic behavior of neurons. In particular the propagation of excitatory postsynaptic potentials is realistic, and we are easily able to emulate such classical synaptic integration models as direction selectivity. We are also able to emulate the backpropagation into the dendrite of single somatic spikes and bursts of spikes. Thus, this silicon dendrite is suitable for incorporation in detailed silicon neurons operating in real-time; in particular for the emulation of forward- and backpropagating electrical activities found in real neurons.

Modeling Alternation to Synchrony with Inhibitory Coupling: A Neuromorphic VLSI Approach

We developed an analog very large-scale integrated system of two mutually inhibitory silicon neurons that display several different stable oscillations. For example, oscillations can be synchronous with weak inhibitory coupling and alternating with relatively strong inhibitory coupling. All oscillations observed experimentally were predicted by bifurcation analysis of a corresponding mathematical model. The synchronous oscillations do not require special synaptic properties and are apparently robust enough to survive the variability and constraints inherent in this physical system. In biological experiments with oscillatory neuronal networks, blockade of inhibitory synaptic coupling can sometimes lead to synchronous oscillations. An example of this phenomenon is the transition from alternating to synchronous bursting in the swimming central pattern generator of lamprey when synaptic inhibition is blocked by strychnine. Our results suggest a simple explanation for the observed oscillatory transitions in the lamprey central pattern generator network: that inhibitory connectivity alone is sufficient to produce the observed transition.

An Improved Silicon Neuron

We describe an improved spiking silicon neuron (SN) [6] that approximates the dynamics of ionic currents of a real nerve cell. The improved version has less circuitry and fewer parameters than previous circuits thereby improving the spiking characteristics. We describe the differential equations governing the revised circuits and use them to explain the spiking properties of the SN. We also describe how to tune the parameters efficiently to bring the neuron quickly into its correct operating regime. The new neurons are sufficiently robust for operation in large networks. We demonstrate their robustness by comparing the neuron’s frequency-current curve between different chips for the same set of parameter values.

Adaptive neural coding dependent on the time-varying statistics of the somatic input current.

It is generally assumed that nerve cells optimize their performance to reflect the statistics of their input. Electronic circuit analogs of neurons require similar methods of self-optimization for stable and autonomous operation. We here describe and demonstrate a biologically plausible adaptive algorithm that enables a neuron to adapt the current threshold and the slope (or gain) of its current-frequency relationship to match the man (or dc offset) and variance (or dynamic range or contrast) of the time-varying somatic input current. The adaptation algorithm estimates the somatic current signal from the spike train by way of the intracellular somatic calcium concentration, thereby continuously adjusting the neurons' firing dynamics. This principle is shown to work in an analog VLSI-designed silicon neuron.

Silicon synaptic conductances.

We have developed compact analog integrated circuits that simulate two synaptic excitatory conductances. A four-transistor circuit captures the dynamics of an excitatory postsynaptic current caused by a real AMPA conductance. A six-transistor circuit simulates the effects of a real voltage-dependent NMDA conductance. The postsynaptic current dynamics are modeled by a current mirror integrator with adjustable gain. The voltage dependence of the silicon NMDA conductance is realized by a differential pair. We show the operation of these silicon synaptic conductances and their integration with the silicon neuron (Mahowald and Douglas, 1991).

An analog memory circuit for spiking silicon neurons.

A simple circuit is described that functions as an analog memory whose state and dynamics are directly controlled by pulsatile inputs. The circuit has been incorporated into a silicon neuron with a spatially extensive dendritic tree as a means of controlling the spike firing threshold of an integrate-and-fire soma. Spiking activity generated by the neuron itself and by other units in a network can thereby regulate the neuron's excitability over time periods ranging from milliseconds to many minutes. Experimental results are presented showing applications to temporal edge sharpening, bistable behavior, and a network that learns in the manner of classical conditioning.

Analogue VLSI Morris-Lecar neuron

The authors have developed a silicon neuron that exhibits properties similar to those of the Morris-Lecar neuron. The Morris-Lecar model is a two-state mathematical model that possesses physiological properties similar to those of actual neurons. The circuit behaviour is analysed, based on the geometry of nullclines in state space and analytical results are compared with experimental data for a circuit implemented in a 2 µm n-well process.