Silicon Neurons Research Articles

Generalized Bio-Plausible Neuron Model with Refractoriness, Frequency Adaptation and Dynamic Threshold

Real biological neurons are dynamical systems that can process a nonlinear, arbitrary input signal with a dynamic threshold voltage, exhibit refractory time, and have a smooth [Formula: see text]–[Formula: see text] curve. This paper presents a generalized bio-plausible neuron model with refractoriness, frequency adaptation, and dynamic threshold. The spiking characteristics of the generalized neuron are enhanced with less circuitry and fewer parameters compared to older circuits. The proposed silicon neuron can generate all known spiking behaviors, just like a biological neuron. The circuit is designed using a 180[Formula: see text]nm standard CMOS process. The entire design uses 22 transistors with a total power consumption of only 2[Formula: see text]nW for a 1[Formula: see text]nA step current at a spike frequency of 122[Formula: see text]Hz. The power consumption and spike frequency rate depend on the input current. The proposed neuron is also capable of displaying both Type I and Type II frequency response characteristics. In addition, our neuron model underwent Monte Carlo simulation with 1000 sample runs to assess its robustness and stability against process variations and uncertainties. The results indicate that the average energy consumption of the proposed neuron model falls within the range of 16[Formula: see text]pJ to 68[Formula: see text]pJ.

Robust compression and detection of epileptiform patterns in ECoG using a real-time spiking neural network hardware framework

Interictal Epileptiform Discharges (IED) and High Frequency Oscillations (HFO) in intraoperative electrocorticography (ECoG) may guide the surgeon by delineating the epileptogenic zone. We designed a modular spiking neural network (SNN) in a mixed-signal neuromorphic device to process the ECoG in real-time. We exploit the variability of the inhomogeneous silicon neurons to achieve efficient sparse and decorrelated temporal signal encoding. We interface the full-custom SNN device to the BCI2000 real-time framework and configure the setup to detect HFO and IED co-occurring with HFO (IED-HFO). We validate the setup on pre-recorded data and obtain HFO rates that are concordant with a previously validated offline algorithm (Spearman’s ρ = 0.75, p = 1e-4), achieving the same postsurgical seizure freedom predictions for all patients. In a remote on-line analysis, intraoperative ECoG recorded in Utrecht was compressed and transferred to Zurich for SNN processing and successful IED-HFO detection in real-time. These results further demonstrate how automated remote real-time detection may enable the use of HFO in clinical practice.

Field-Programmable Analog Array Implementation of Neuromorphic Silicon Neurons with Fractional Dynamics

Silicon neurons are bioinspired circuits with the capability to reproduce the modulation through pulse-frequency observed in real neurons. They are of particular interest in closed-loop schemes to encode the control signal into pulses. This paper proposes the analog realization of neuromorphic silicon neurons with fractional dynamics. In particular, the fractional-order (FO) operator is introduced into classical neurons with the intention of reproducing the adaptation that has been observed experimentally in real neurons, which is the variation in the firing frequency even when considering a constant or periodic incoming stimulus. For validation purposes, simulations using a field-programmable analog array (FPAA) are performed to verify the behavior of the circuits.

Leaky-integrate-fire neuron based on vertically extended drain Si[formula omitted]Ge[formula omitted] source TFET: Ultra-energy-efficient and high speed design

This article investigates the performance of a vertically extended drain double gate Si1−x Gex source tunnel field effect transistor (VD-DG-Si1−x Gex S-TFET) as a leaky integrate-and-fire (LIF) neuron. The proposed VD-DG-Si1−x Gex S-TFET structure has been designed and optimized by deploying the commercially available Silvaco TCAD. The LIF neuron using VD-DG-Si1−x Gex S-TFET requires a low spiking threshold voltage (i.e. 0.20 V) which is 5x, 3x, 5x, 1.3x, 1.55x, 7.5x, and 1.44x times less in comparison to MOSFET, Bulk FinFET, phase change device, SOI MOSFET, DG-JLFET, silicon nanowire, and DL-TFET silicon neuron. The proposed device based neuron demonstrates the least spiking energy (177 ZJ) reported to date which is 18192 times less as compared to BTBT based PDSOI MOSFET neuron. The threshold value of current is achieved at 0.20 V drain voltage which is 15x, 14x, 10x, and 1.5x less as compared to FinFET, PD-SOI MOSFET, LBIMOS, and DL-TFET, respectively. Moreover, the effects of gate metal work function, germanium mole fraction, and temperature on the spike current variations have also been investigated. Here, impact ionization is a key method for generating a neuron spike due to holes accumulated in the potential well of VD-DG-Si1−xGex S-TFET. In addition, a LIF neuron based on VD-DG-Si0.5Ge0.5 S-TFET device exhibits a 9 THz spiking frequency which is approximately 12 times higher than real nerves present in the human body. This work shows a remarkable reduction in the power consumption and the proposed device neuron is a potential start-up solution for a large scale spiking neural networks (SNN) implementation because of its better performance and compact circuitry.

Reliability-aware design of Integrate-and-Fire silicon neurons

Variation in CMOS device parameters due to reliability issues like Bias Temperature Instability (BTI) and Hot Carrier Injection (HCI), etc., has posed serious performance concerns in various digital and analog/mixed-signal circuit designs, which include neuromorphic circuits. CMOS-based neuromorphic circuits, also known as silicon neurons (SiNs), are designed to emulate the electrophysiological behavior of biological neurons. Neuromorphic systems are used to learn and adapt in various applications like image processing and classification, wearable/implantable systems, robotics, etc. that require high performance. It is therefore, important to analyze neuromorphic circuits performance over their lifetime. This is achieved by identifying the specific transistors affecting circuit performance and to come up with workable ways to solve these problems. In this work, we have investigated the combined effect of NBTI and HCI on two types of Integrate-and-Fire (I&F) SiNs, Axon-Hillock (AH) and Simplified Leaky Integrate-and-Fire (SLIF) circuits, using key performance parameters. Novel reliability-aware AH and SLIF circuits are proposed to mitigate the reliability issues. The proposed reliability-aware designs show negligible deviations in the performance parameters after degradation. The time-zero process variability analysis is also carried out for the proposed reliability-aware SiNs. The power consumption of existing and proposed reliability-aware neuron circuits is analyzed and compared.

Learning inverse kinematics using neural computational primitives on neuromorphic hardware

Current low-latency neuromorphic processing systems hold great potential for developing autonomous artificial agents. However, the variable nature and low precision of the underlying hardware substrate pose severe challenges for robust and reliable performance. To address these challenges, we adopt hardware-friendly processing strategies based on brain-inspired computational primitives, such as triplet spike-timing dependent plasticity, basal ganglia-inspired disinhibition, and cooperative-competitive networks and apply them to motor control. We demonstrate this approach by presenting an example of robust online motor control using a hardware spiking neural network implemented on a mixed-signal neuromorphic processor, trained to learn the inverse kinematics of a two-joint robotic arm. The final system is able to perform low-latency control robustly and reliably using noisy silicon neurons. The spiking neural network, trained to control two joints of the iCub robot arm simulator, performs a continuous target-reaching task with 97.93% accuracy, 33.96 ms network latency, 102.1 ms system latency, and with an estimated power consumption of 26.92 μW during inference (control). This work provides insights into how specific computational primitives used by real neural systems can be applied to neuromorphic computing for solving real-world engineering tasks. It represents a milestone in the design of end-to-end spiking robotic control systems, relying on event-driven sensory encoding, neuromorphic processing, and spiking motor control.

Brain-inspired methods for achieving robust computation in heterogeneous mixed-signal neuromorphic processing systems

Abstract Neuromorphic processing systems implementing spiking neural networks with mixed signal analog/digital electronic circuits and/or memristive devices represent a promising technology for edge computing applications that require low power, low latency, and that cannot connect to the cloud for off-line processing, either due to lack of connectivity or for privacy concerns. However, these circuits are typically noisy and imprecise, because they are affected by device-to-device variability, and operate with extremely small currents. So achieving reliable computation and high accuracy following this approach is still an open challenge that has hampered progress on the one hand and limited widespread adoption of this technology on the other. By construction, these hardware processing systems have many constraints that are biologically plausible, such as heterogeneity and non-negativity of parameters. More and more evidence is showing that applying such constraints to artificial neural networks, including those used in artificial intelligence, promotes robustness in learning and improves their reliability. Here we delve even more into neuroscience and present network-level brain-inspired strategies that further improve reliability and robustness in these neuromorphic systems: we quantify, with chip measurements, to what extent population averaging is effective in reducing variability in neural responses, we demonstrate experimentally how the neural coding strategies of cortical models allow silicon neurons to produce reliable signal representations, and show how to robustly implement essential computational primitives, such as selective amplification, signal restoration, working memory, and relational networks, exploiting such strategies. We argue that these strategies can be instrumental for guiding the design of robust and reliable ultra-low power electronic neural processing systems implemented using noisy and imprecise computing substrates such as subthreshold neuromorphic circuits and emerging memory technologies.

An Analytical MOS Device Model With Mismatch and Temperature Variation for Subthreshold Circuits

Subthreshold analog circuits are attractive for low-power, large-scale neuromorphic systems. However, subthreshold currents are exponentially sensitive to temperature and device mismatch, and a compact model that accounts for these effects is needed. We develop an analytical compact model with mismatch and temperature variation for subthreshold MOS devices. The model only requires an initial set of Monte Carlo (MC) simulations on individual devices for parameter extraction. Then the designer can use its parameterized analytical expressions for circuit design, instead of running repeated MC simulations on large circuits. We apply this model to a subthreshold current mirror design example. Good agreement between the developed model and Spectre simulations is achieved in a 28-nm fully-depleted silicon-on-insulator (FDSOI) process. The model is general and can also guide the design of other subthreshold circuits, such as low-power silicon neurons. It has been used to design Braindrop, the first neuromorphic chip programmed at a high level of abstraction.

A 5.3 pJ/Spike CMOS Neural Array Employing Time-Modulated Axon-Sharing and Background Mismatch Calibration Techniques

Inspired by the human brain, spiking neuron networks are promising to realize energy-efficient and low-latency neuromorphic computing. However, even state-of-the-art silicon neurons are orders of magnitude worse than biological neurons in terms of area and power consumption due to the limitations. Moreover, limited routing in typical CMOS processes is another challenge for realizing the fully-parallel high-throughput synapse connections compared to biological synapses. This paper presents an SNN circuit that utilizes resource-sharing techniques to address the two challenges. Firstly, a comparator sharing neuron circuit with a background calibration technique is proposed to shrink the size of a single neuron without performance degradation. Secondly, a time-modulated axon-sharing synapse system is proposed to realize a fully-parallel connection with limited hardware overhead. To validate the proposed approaches, a CMOS neuron array is designed and fabricated under a 55-nm process. It consists of 48 LIF neurons with 3125 neurons/mm 2 area density, power consumption of 5.3 pJ/spike, and equivalent 2304 fully parallel synapses providing a unit throughput of 5500 events/s/neuron. It proves the proposed approaches are promising to realize a high-throughput high-efficiency SNN with CMOS technology.

Piecewise quadratic neuron model: A tool for close-to-biology spiking neuronal network simulation on dedicated hardware.

Spiking neuron models simulate neuronal activities and allow us to analyze and reproduce the information processing of the nervous system. However, ionic-conductance models, which can faithfully reproduce neuronal activities, require a huge computational cost, while integral-firing models, which are computationally inexpensive, have some difficulties in reproducing neuronal activities. Here we propose a Piecewise Quadratic Neuron (PQN) model based on a qualitative modeling approach that aims to reproduce only the key dynamics behind neuronal activities. We demonstrate that PQN models can accurately reproduce the responses of ionic-conductance models of major neuronal classes to stimulus inputs of various magnitudes. In addition, the PQN model is designed to support the efficient implementation on digital arithmetic circuits for use as silicon neurons, and we confirm that the PQN model consumes much fewer circuit resources than the ionic-conductance models. This model intends to serve as a tool for building a large-scale closer-to-biology spiking neural network.

An organic synaptic circuit: toward flexible and biocompatible organic neuromorphic processing

In the nervous system synapses play a critical role in computation. In neuromorphic systems, biologically inspired hardware implementations of spiking neural networks, electronic synaptic circuits pass signals between silicon neurons by integrating pre-synaptic voltage pulses and converting them into post-synaptic currents, which are scaled by the synaptic weight parameter. The overwhelming majority of neuromorphic systems are implemented using inorganic, mainly silicon, technology. As such, they are physically rigid, require expensive fabrication equipment and high fabrication temperatures, are limited to small-area fabrication, and are difficult to interface with biological tissue. Organic electronics are based on electronic properties of carbon-based molecules and polymers and offer benefits including physical flexibility, low cost, low temperature, and large-area fabrication, as well as biocompatibility, all unavailable to inorganic electronics. Here, we demonstrate an organic differential-pair integrator synaptic circuit, a biologically realistic synapse model, implemented using physically flexible complementary organic electronics. The synapse is shown to convert input voltage spikes into output current traces with biologically realistic time scales. We characterize circuit’s responses based on various synaptic parameters, including gain and weighting voltages, time-constant, synaptic capacitance, and circuit response due to inputs of different frequencies. Time constants comparable to those of biological synapses and the neurons are critical in processing real-world sensory signals such as speech, or bio-signals measured from the body. For processing even slower signals, e.g., on behavioral time scales, we demonstrate time constants in excess of two seconds, while biologically plausible time constants are achieved by deploying smaller synaptic capacitors. We measure the circuit synaptic response to input voltage spikes and present the circuit response properties using custom-made circuit simulations, which are in good agreement with the measured behavior.

Comparative Research of Neuron Circuits

Abstract: Spiking neurons can be implemented in hardware, for example, to model large neural systems, simulate real-time behaviour, and interface bi-directionally between brains and machines. Circuit solutions used to implement silicon neuron circuits depend on the application requirements. Various neuron circuits are presented in this thesis, including spike-event generators (Axon Hillock neuron circuits), above-threshold neuron circuits (Quadratic Integrate and Fire neuron circuits), and differential pair integrator circuits. Cadence's tool simulates these circuits using 180nm technology. Comparing these circuits is based on their working properties and simulation results, and their features are demonstrated with experiments.

Silicon Modeling of Spiking Neurons With Diverse Dynamic Behaviors

Since spiking neural networks (SNNs) can effectively simulate the information processing mechanism of the biological cortex, they are expected to bridge the gap between neuroscience and machine learning. The hardware simulation of large-scale SNNs requires a simple and versatile silicon neuron model framework. In this article, a spiking neuron circuit as the core device of SNNs is presented. The proposed neuron circuit can mimic the dynamics of different types of biological neurons by adjusting the bias voltage. In order to facilitate the implementation of the spiking neuron circuit based on complementary metal-oxide-semiconductor (CMOS) and reduce the overhead of the circuit area, a modified Mihalas–Niebur (MN) mathematical model is adopted. The improved MN model is biologically plausible and can still successfully display all dynamic behaviors observed in biology. The function of the proposed neuron circuit has been verified by the phase diagram analysis method. The simulation results show the designed neuron circuit can successfully replicate 15 of the 20 firing patterns exhibited by the biological cortex, which proves that the neuron can act as a universal spiking neuron in very large-scale integrated circuit (VLSI) neuromorphic networks.

Mathematical and Circuit Level Analysis Interpretation and Recommendations on Neuron Models

Contrary to von Neumann computer architecture, neuromorphic computing is a biologically inspired method for building several sorts of brain-inspired computers. This computer technology uses silicon neurons and synapses to solve difficult machine learning and AI challenges. The goal of neuromorphic computing is to build a brain-like ability to compute, learn, and adapt. Building an appropriate neuroscience model, establishing a new architecture, modeling new devices, finding new materials for the devices, programming framework, and applications for these neuromorphic devices are major technological challenges. This study covers numerous neuron models from Hodgkin–Huxley to I&F, mathematical equations, circuit level analysis and motivations for neuromorphic computing. Here some of the most useful silicon neuron models are discussed in terms of biological plausibility, computational efficiency, and temperature dependency. This survey shows that more than 52 transistors make up the silicon HH neuron, which occupies less than 0.01[Formula: see text][Formula: see text] and consumes 60[Formula: see text]uW of power. On the other hand, an I&F neuron needs less than 20 transistors, occupies 442[Formula: see text][Formula: see text] and consumes 40[Formula: see text]pW of power.

Central Nervous System: Overall Considerations Based on Hardware Realization of Digital Spiking Silicon Neurons (DSSNs) and Synaptic Coupling

The Central Nervous System (CNS) is the part of the nervous system including the brain and spinal cord. The CNS is so named because the brain integrates the received information and influences the activity of different sections of the bodies. The basic elements of this important organ are: neurons, synapses, and glias. Neuronal modeling approach and hardware realization design for the nervous system of the brain is an important issue in the case of reproducing the same biological neuronal behaviors. This work applies a quadratic-based modeling called Digital Spiking Silicon Neuron (DSSN) to propose a modified version of the neuronal model which is capable of imitating the basic behaviors of the original model. The proposed neuron is modeled based on the primary hyperbolic functions, which can be realized in high correlation state with the main model (original one). Really, if the high-cost terms of the original model, and its functions were removed, a low-error and high-performance (in case of frequency and speed-up) new model will be extracted compared to the original model. For testing and validating the new model in hardware state, Xilinx Spartan-3 FPGA board has been considered and used. Hardware results show the high-degree of similarity between the original and proposed models (in terms of neuronal behaviors) and also higher frequency and low-cost condition have been achieved. The implementation results show that the overall saving is more than other papers and also the original model. Moreover, frequency of the proposed neuronal model is about 168 MHz, which is significantly higher than the original model frequency, 63 MHz.

Implementation and Feedback Control Tuning of an Analog Izhikevich Neuron Circuit

Analog circuits have proven to be a reliable medium for neuromorphic architectures in silicon, capable of emulating parts of the brain’s computational processes. Information in the brain is shared between neurons in the form of spikes, where a neuron’s soma emits a voltage signal after integrating multiple synaptic input currents. To preserve the quality of this information in a rate-based protocol, it is important that a postsynaptic neuron is able to adapt its firing rate to some desired or expected rate, especially in a noisy environment. This paper presents an analog Izhikevich neuron circuit and a proof-of-concept tuning algorithm that adjusts the neuron’s spike rate using proportional feedback control. The neuron circuit is implemented using discrete surface-mount components on a custom printed circuit board, and its output spike pattern is modified by adjusting one of the neuron’s four voltage parameters. Adjusting the voltage parameters gives a neuromorphic system designer the ability to calibrate these silicon neurons in the presence of noise or component imperfections, ensuring a baseline configuration where all neurons exhibit the same, expected spike response given the same input.

Robust neuromorphic coupled oscillators for adaptive pacemakers

Neural coupled oscillators are a useful building block in numerous models and applications. They were analyzed extensively in theoretical studies and more recently in biologically realistic simulations of spiking neural networks. The advent of mixed-signal analog/digital neuromorphic electronic circuits provides new means for implementing neural coupled oscillators on compact, low-power, spiking neural network hardware platforms. However, their implementation on this noisy, low-precision and inhomogeneous computing substrate raises new challenges with regards to stability and controllability. In this work, we present a robust, spiking neural network model of neural coupled oscillators and validate it with an implementation on a mixed-signal neuromorphic processor. We demonstrate its robustness showing how to reliably control and modulate the oscillator’s frequency and phase shift, despite the variability of the silicon synapse and neuron properties. We show how this ultra-low power neural processing system can be used to build an adaptive cardiac pacemaker modulating the heart rate with respect to the respiration phases and compare it with surface ECG and respiratory signal recordings from dogs at rest. The implementation of our model in neuromorphic electronic hardware shows its robustness on a highly variable substrate and extends the toolbox for applications requiring rhythmic outputs such as pacemakers.

Emerging Artificial Neuron Devices for Probabilistic Computing.

In recent decades, artificial intelligence has been successively employed in the fields of finance, commerce, and other industries. However, imitating high-level brain functions, such as imagination and inference, pose several challenges as they are relevant to a particular type of noise in a biological neuron network. Probabilistic computing algorithms based on restricted Boltzmann machine and Bayesian inference that use silicon electronics have progressed significantly in terms of mimicking probabilistic inference. However, the quasi-random noise generated from additional circuits or algorithms presents a major challenge for silicon electronics to realize the true stochasticity of biological neuron systems. Artificial neurons based on emerging devices, such as memristors and ferroelectric field-effect transistors with inherent stochasticity can produce uncertain non-linear output spikes, which may be the key to make machine learning closer to the human brain. In this article, we present a comprehensive review of the recent advances in the emerging stochastic artificial neurons (SANs) in terms of probabilistic computing. We briefly introduce the biological neurons, neuron models, and silicon neurons before presenting the detailed working mechanisms of various SANs. Finally, the merits and demerits of silicon-based and emerging neurons are discussed, and the outlook for SANs is presented.

Low‐Current Sensing Analog‐to‐Digital Converter with Tuneable Resolution for Biomedical Applications

A novel low‐power, tuneable resolution and low‐current sensing analog‐to‐digital converter is proposed in this paper. The proposed architecture consists of silicon neurons along with digital circuits. The architecture is tuned for input signal ranging from 100 nA to 3.3 μA with power supply of 1 V/3.3 V for digital blocks and silicon neurons respectively. The design is simulated using 0.18 μm CMOS 1P4M triple well process of Tower Jazz Semiconductor's technology. Total power consumption of the circuit is 98.8 μW and achieves FoM of 14.74 pJ/Conv for 8‐bits of operation. © 2021 Institute of Electrical Engineers of Japan. Published by Wiley Periodicals LLC.

Role of Noise in Spontaneous Activity of Networks of Neurons on Patterned Silicon Emulated by Noise–activated CMOS Neural Nanoelectronic Circuits

Background noise in biological cortical microcircuits constitutes a powerful resource to assess their computational tasks, including, for instance, the synchronization of spiking activity, the enhancement of the speed of information transmission, and the minimization of the corruption of signals. We explore the correlation of spontaneous firing activity of ≈ 100 biological neurons adhering to engineered scaffolds by governing the number of functionalized patterned connection pathways among groups of neurons. We then emulate the biological system by a series of noise-activated silicon neural network simulations. We show that by suitably tuning both the amplitude of noise and the number of synapses between the silicon neurons, the same controlled correlation of the biological population is achieved. Our results extend to a realistic silicon nanoelectronics neuron design using noise injection to be exploited in artificial spiking neural networks such as liquid state machines and recurrent neural networks for stochastic computation.