Midgap Of Silicon Research Articles

Origin of weak Fermi level pinning at the graphene/silicon interface

The mechanisms governing the formation of Schottky barriers at graphene/hydrogen-passivated silicon interfaces where the graphene plays the role of a two-dimensional (2D) metal electrode have been investigated by means of x-ray photoemission spectroscopy and density functional theory (DFT) calculations. To control the graphene work function without altering either the structure or the band dispersion of graphene we used a method that consists in depositing small amounts of gold forming clusters on the graphene/hydrogen-passivated silicon system under an ultra-high-vacuum environment. We observe from experimental measurements that the Fermi level is mainly free from pinning at the graphene/hydrogen-silicon interface whereas for a semi-infinite metal on silicon the Fermi level is almost fully pinned. This alleviation of the Fermi level pinning observed with the graphene layer is explained by DFT calculations showing that the graphene and the semiconductor are decoupled and that the metal-induced gap states (MIGS) density at the silicon midgap at the interface is very low ($l5\ifmmode\times\else\texttimes\fi{}{10}^{10}\phantom{\rule{0.16em}{0ex}}\mathrm{states}/(\mathrm{eV}\phantom{\rule{0.28em}{0ex}}\mathrm{c}{\mathrm{m}}^{2})$]. The important conclusion that stems from the DFT results analysis is that the low MIGS density at the semiconductor midgap is related to the 2D nature of the graphene layer. More precisely, the MIGS density is low owing to the lack of propagating states perpendicular to the graphene layer. This finding brings important information to understand the mechanisms that govern the formation and the electronic properties of Schottky barriers at 2D-metal/three-dimensional-semiconductor interfaces.

Insights into the reliability of Ni/Cu plated p-PERC silicon solar cells

Selective laser ablation of dielectric layers in combination with plated Ni/Cu/Ag contacts have been investigated by many photovoltaic researchers. Despite that there has been quite some practical progress on improved processing, the reliability of plated Ni/Cu/Ag cells still needs further insight and understanding. In this paper, the impact of laser induced defects that result from a ps-laser (wavelength 355nm) ablation on the performance of p-type PERC cells has been studied. A thermal stress experiment at 235oC is applied. It is shown that the defects formed during the laser ablation process do indeed decrease the cell performance. A higher laser fluence results in lower fill factor and therefore lower efficiency. Moreover, the cells with higher laser fluence ablation degrade faster compared to the cells which had lower laser fluence to open the dielectric layer. The second part of the paper focuses on characterization of the p-n junction of the laser ablated cells by Deep Level Transient Spectroscopy (DLTS) before and after thermal ageing. A hole trap around 80K was found for all samples, which is related to point defects induced during the cell processing. A broad peak around 200K observed for the ablated cells with high laser fluence could correspond to dislocations induced by the laser ablation. This peak is shifted to higher energy (closer to the silicon mid-gap) after annealing, which may be due to impurity decoration during the annealing.

Deep levels in silicon–oxygen superlattices

This work reports on the deep levels observed in Pt/Al2O3/p-type Si metal-oxide-semiconductor capacitors containing a silicon–oxygen superlattice (SL) by deep-level transient spectroscopy. It is shown that the presence of the SL gives rise to a broad band of hole traps occurring around the silicon mid gap, which is absent in reference samples with a silicon epitaxial layer. In addition, the density of states of the deep layers roughly scales with the number of SL periods for the as-deposited samples. Annealing in a forming gas atmosphere reduces the maximum concentration significantly, while the peak energy position shifts from close-to mid-gap towards the valence band edge. Based on the flat-band voltage shift of the Capacitance–Voltage characteristics it is inferred that positive charge is introduced by the oxygen atomic layers in the SL, indicating the donor nature of the underlying hole traps. In some cases, a minor peak associated with Pb dangling bond centers at the Si/SiO2 interface has been observed as well.

Deep-level transient spectroscopy of Al/a-Si:H/c-Si structures for heterojunction solar cell applications

A Deep-Level Transient Spectroscopy study is performed on Metal-Insulator-Semiconductor capacitors with a 70 nm amorphous silicon (a-Si:H) passivation layer, in order to study the electrically active defects present at the n- or p-type crystalline silicon (c-Si)/a-Si:H heterojunction. Trap filling kinetics identify two types of traps, namely, Pb0 dangling bond centers at the Si(100) interface and similar D centers in the a-Si:H, which are in close proximity to the interface and giving rise to a dominant peak around silicon midgap. The distinction between both kinds of deep levels is based on the carrier capture behavior, which is more point-defect-like for the Pb0 centers and varies according to the logarithm of the voltage pulse duration for the D defects, indicating capture of majority carriers from the substrate by tunneling into a-Si:H, the densities of which are correlated with capacitance-voltage measurements. This directly demonstrates that the recombination properties of the c-Si/a-Si:H interface are both determined by Pb0 and D defect states.

Influence of structural defects on thermostability and radiation sensitivity of Si MOSFET dosimeters

The metal oxide semiconductor field effect transistor (MOSFET) dosimeters have recently become commercially available. For this reason, it is not surprising that the study of radiation interactions with MOS materials, devices, and circuits has been a major theme of many articles. The purpose of this study was to investigate the influence of structural defects on thermostability and radiation sensitivity of Si MOSFET dosimeters. It was shown that the near-surface layers of silicon have a complex defective structure which consists from the disordered layer of silicon and the layer of dislocation networks. Grain boundaries of disordered layer form additional energy levels close to the midgap of silicon. These states are ionized under radiation effect and form positive charge. This positive radiation-induced charge becomes additional to the oxide charge and it changes (increases) radiation sensitivity of Si MOSFET detectors. However, these states are the additional source of charge carriers under temperature increasing and lead to changing of detector’s parameters.

Analysis of trap generation during programming/erasing cycling in silicon nanocrystal memory devices

Trap generation of a nonvolatile silicon-nanocrystal memory during Fowler–Nordheim programming/erasing (P/E) cycling is analyzed using the combination of capacitance–voltage and current–voltage measurements. With increasing the number of P/E cycles, the flatband voltage decreases due to hole trapping in the accumulation; the threshold voltage increases due to electron trapping in the inversion. The generation of hole and electron trapping is explained by an anode hole injection mechanism and a cathode injection mechanism, respectively. It is found that the magnitudes of hole and electron trapping depend on both Fowler–Nordheim programming and erasing bias conditions. Sweeping gate voltage from strong accumulation to strong inversion, a gate current spike appears near the silicon midgap voltage in cycled devices and is attributed to the recombination between trapped holes in the tunneling oxide and tunneling electrons from the acceptor interface states above the intrinsic Fermi level.

Compositional dependence of work function and Fermi level position of the HfN x/SiO 2 system

In situ Kelvin Probe (KP) measurements performed on HfN x showed an increase of the vacuum work function as a function of N content from a value of 3.9 eV (silicon conduction band edge) for pure Hf to a value of 5 eV (silicon valence band edge) for x ∼ 2. In contrast, capacitance–voltage ( C– V) measurements showed that the effective work function increased only until x < 1 and saturated around a value of 4.6 eV (silicon midgap). This behavior is attributed to Fermi level pinning, which is probably due to oxidation of the HfN x during the reactive sputtering deposition step.

Effective passivation of slow interface states at the interface of single crystalline Gd2O3 and Si(100)

The as-grown single crystalline Gd2O3 thin film on Si(100) substrate suffers from flatband voltage instability and large hysteresis which are possibly due to the intrinsic dangling bonds induced by the existing binding mismatch at the Gd2O3∕Si(100) interface. The instability of flatband voltage and hysteresis of Pt∕Gd2O3∕Si and W∕Gd2O3∕Si structures can be fully eliminated by the introduction of traditional forming gas annealing with proper process optimization. Both optimized metal-oxide-semiconductor structures show negligible hysteresis with the interface state at the magnitude order of 1011∕cm2eV at the midgap of silicon and can be considered for the future of complementary metal oxide semiconductor devices.

Influences of Trap States at Metal/Semiconductor Interface on Metallic Source/Drain Schottky-Barrier MOSFET

The electrical properties of metallic junction diodes and metallic source/drain (S/D) Schottky barrier metal-oxide-semiconductor fieldeffect transistor (SB-MOSFET) were simulated. By using the abrupt metallic junction at the S/D region, the short-channel effects in nano-scaled MOSFET devices can be effectively suppressed. Particularly, the effects of trap states at the metal-silicide/silicon interface of S/D junction were simulated by taking into account the tail distributions and the Gaussian distributions at the silicon band edge and at the silicon midgap, respectively. As a result of device simulation, the reduction of interfacial trap states with Gaussian distribution is more important than that of interfacial trap states with tail distribution for improving the metallic junction diodes and SBMOSFET. It is that a forming gas annealing after silicide formation significantly improved the electrical properties of metallic junction devices.

Integration of HfxTayN Metal Gate Electrode with High-k Gate Dielectric in MOS Devices

In this work, the composition effects of hafnium (Hf) and tantalum (Ta) in HfxTayN metal gate on the thermal stability of metal-oxide-semiconductor (MOS) devices were investigated. The work function of the HfxTayN metal gate can reach a value of ~4.6 eV (midgap of silicon) by suitably adjusting the Hf and Ta compositions. In addition, with a small amount of Hf incorporated into a TaN metal gate, excellent thermal stability of electrical properties, including the work function, the equivalent oxide thickness (EOT), interface trap density and defect generation rate characteristics, can be achieved after a post-metal anneal up to 950 oC for 45 s. Experimental results indicate that Ta-rich HfxTayN is a promising metal gate for advanced MOS devices.

Thermal stability of Hf/sub x/Ta/sub y/N metal gate electrodes for advanced MOS devices

In this letter, the composition effects of hafnium (Hf) and tantalum (Ta) in Hf/sub x/Ta/sub y/N metal gate on the thermal stability of MOS devices were investigated. The work function of the Hf/sub x/Ta/sub y/N metal gate can reach a value of /spl sim/4.6 eV (midgap of silicon) by suitably adjusting the Hf and Ta compositions. In addition, with a small amount of Hf incorporated into a TaN metal gate, excellent thermal stability of electrical properties, including the work function, the equivalent oxide thickness, interface trap density and defect generation rate characteristics, can be achieved after a post-metal anneal up to 950/spl deg/C for 45 s. Experimental results indicate that Ta-rich Hf/sub x/Ta/sub y/N is a promising metal gate for advanced MOS devices.

Ultrathin HfO2 gate dielectric grown by plasma-enhanced chemical vapor deposition using Hf[OC(CH3)3]4 as a precursor in the absence of O2

Hafnium oxide thin films for use in a gate dielectric were deposited at 300 °C on p-type Si(100) substrates using a Hf[OC(CH3)3]4 precursor in the absence of oxygen by plasma-enhanced chemical vapor deposition. A comparison of films deposited in the absence and presence of oxygen indicated that oxygen was an important determinant in the electrical properties of HfO2 films, which were subsequently annealed in N2 and O2 ambients. The capacitance equivalent oxide thickness of the as-deposited Pt/HfO2/Si capacitor was approximately 17 Å and abruptly increased at an annealing temperature of 800 °C in both N2 and O2 ambients. The hysteresis of the as-deposited gate dielectric was quite small, about 40 mV, and that of the gate dielectric annealed at 800 °C in an O2 ambient was reduced to a negligible level, about 20 mV. The interface trap density of the Pt/HfO2/Si capacitors was approximately 1012 eV−1 cm−2 near the silicon midgap. The leakage current densities of the as-deposited Pt/HfO2/Si capacitor and those annealed at 800 °C in N2 and O2 were approximately 8 × 10−4, 8 × 10−5, and 3 × 10−7 A/cm2 at –1 V, respectively.

Tantalum nitride metal gate FD-SOI CMOS FETs using low resistivity self-grown bcc-tantalum layer

A tantalum nitride (TaNx) metal gate complementary metal oxide semiconductor (CMOS) technology using low-resistivity (/spl sim/15 /spl mu//spl Omega/cm), bcc (body-centered-cubic)-phase tantalum metal layer has been developed, featuring low-temperature processing below 550/spl deg/C except for gate oxide formation. It was found for the first time that TaNx works not only as a buffer layer which prevents tantalum metal film and gate oxide film from reacting with each other, but also as a seed layer which helps self-growth of bcc-phase tantalum films by hetero-epitaxy. Furthermore, we have demonstrated that the work function of TaNx gate is close to midgap of silicon, hence similar to titanium nitride (TiNx) gate. We have also demonstrated that MOS capacitors on bulk and fully-depleted silicon-on-insulator (FD-SOI) CMOS with TaNx/bcc-Ta/TaNx stacked metal gate structure have excellent electrical characteristics and that the ring-oscillator fabricated using the stacked metal gate CMOS can be operated successfully with 3.8 nm-thickness gate oxide.

Nitrogen induced states at the CNx/Si interface

The deposition of carbon nitride (CNx) films onto n-type silicon wafers by rf magnetron sputtering at room temperature produces insulating films suitable for electronic applications. The traps at the CNx/Si interface may hamper the creation of electronic devices especially in VLSI applications. While amorphous carbon films have been studied for that purpose, the introduction of nitrogen inside the growth chamber adds an extra parameter in the process. CNx films were grown with the N2 concentration ranging between 1 and 25%. The effect of various N2 concentrations on the interface states is investigated in the present work. The interface states were characterized by admittance spectroscopy on metal-insulator-semiconductor (MIS) devices created by the deposition of A1 contacts. The density of interface states (Dit) and the corresponding time constants were obtained by the conductance technique. The Dit was found to extend between 5.5×1012 and 2.0×1013 eV−1 cm−2 depending on the N2 concentration. Annealing at 350°C reduced these values. Typical values for the time constants were around 10−4 s indicating that the traps are located close to the silicon midgap.

A study on the capacitance–voltage characteristics of metal-Ta2O5-silicon capacitors for very large scale integration metal-oxide-semiconductor gate oxide applications

In this work, the capacitance–voltage characteristics of Au/Ta2O5/Si capacitors are studied. The Ta2O5 films are deposited by plasma-enhanced chemical vapor deposition system. Constant voltage stress is applied to the Ta2O5 capacitors. The flatband voltage VFB is measured before and after the constant voltage stress. The flatband voltage shift due to the stress is explained by the trapping of electrons and holes. An interface trapped charge density (Dit) about 2×1011 eV−1 cm−2 in the midgap of silicon is extracted by using the conductance method. The discharging transient current after a constant voltage stress is measured and correlated with the electron and hole trapping. The trapped electron and hole densities in Ta2O5 are calculated by using the tunneling front model. The VFB shift and the discharging transient currents are explained based on the energy band diagram of the metal/Ta2O5/silicon system.

Evaluation of the interface state density from light induced effects onI–U characteristics of Schottky diodes

The change of forward I–U characteristics of an Al/Si Schottky diode upon illumination at low temperature is observed. The current decays rapidly with time immediately after the illumination is switched off, followed by a slow change or saturation which is bias dependent. Light induced effect (Staebler-Wronski effect) on the I–U dark curves allows us to determine the incremental dark capacitance Cdark which is found to be equal to the interface capacitance at low forward voltages. The density of interface traps Ds obtained from Cdark and that evaluated from the light induced effect on the dark conductivity for the diode under investigation have approximately the same values. Both techniques show the existence of a peak in the interface density around 0.47 eV below silicon mid-gap.

Record low SiO2/Si interface state density for low temperature oxides prepared by direct plasma-enhanced chemical vapor deposition

A new process has been developed to achieve a very low SiO2/Si interface state density for low temperature deposited oxides on silicon substrates. The technique involves direct plasma-enhanced chemical vapor deposition (PECVD), with appropriate growth conditions, followed by a photo-assisted anneal. Approximately 500-Å-thick SiO2 layers, deposited on Si by PECVD at 250 °C with 0.02 W/cm−2 rf power, then covered with an evaporated thin aluminum layer, and finally subjected to a photo-assisted anneal in forming gas ambient at 350 °C, resulted in interface state density, (Dit), in the range of 1–4×1010 cm−2 eV−1 near midgap of silicon. The best Dit value achieved in this study was 1.1×1010 cm−2 eV−1, which sets a new record for the lowest Dit for the PECVD oxides fabricated to date. Detailed analysis showed that the PECVD deposition conditions, photo-assisted anneal, forming gas ambient, and the presence of an aluminum layer on top of the oxides during the anneal, all contributed to this extremely low value of Dit.

Conductance technique measurements of the density of interface states between ZnS:Mn and p-silicon

Capacitance and conductance measurements are presented for dc-driven Au/ZnS:Mn/p-Si electroluminescence metal-insulator-semiconductor (MIS) devices, where the ZnS:Mn films are deposited by radio frequency sputtering. Stable dc operation is achieved by introducing oxygen into the film during deposition and subsequently annealing. The effect of the post-deposition annealing upon the density of states at the ZnS:Mn/p-Si interface is investigated. As deposited, the devices show unusual MIS C-V characteristics, that indicate a very high interface state density. Annealing at 700 °C, normal C-V characteristics are observed, indicating that the very high density of states is greatly reduced. For these films the conductance technique has been used to measure the density of states at the interface between the ZnS:Mn and p-Si. The statistical model is found to describe most accurately the interface state conductance response. The interface state density consists of a tail of states that varies between 3.7×1013 cm−2 eV−1 at the silicon Fermi level and 1.1×1013 cm−2 eV−1 at the silicon mid-gap. A small peak is superimposed upon this tail at (−0.16±0.01) eV below mid-gap. The tail of states is believed to be intrinsic to the ZnS:Mn/p-Si interface, but evidence suggests that the small peak is due to the presence of oxygen, which is shown by secondary-ion mass spectrometry analysis to accumulate at the interface after annealing at 700 °C. It seems likely that the very high density of interface states in as deposited devices is a consequence of a plasma damage to the silicon surface during growth, creating defects such as silicon dangling bonds. One possible explanation for the decrease in this density is that by annealing at 700 °C, oxygen in the bulk of the film diffuses to the interface, where it mops up these defects by forming compounds such as SiOx. A simpler model of interface recrystallization is also suggested. The doping density in the depletion region of the silicon is calculated as (7.5±0.5)×1014 cm−3, and the interface state capture cross section for holes is found to have mean value of approximately 10−15 cm−2.

Detection of interface and volume traps in very thin oxide MOS structures using DLTS, quasi-static and conductance measurements

Electrically active interface and volume traps in CrSiO 2Si ( p-type) capacitors with very thin oxide layers (3.5 and 8.5 nm) are studied. The determination of the interface trap parameters is performed using three techniques; quasi-static, conductance and deep level transient spectroscopy (DLTS). Their densities are typically in the range of 10 10 eV −1 cm −2 near the silicon midgap for 8.5 nm thick oxide layers and of 10 11 eV −1 cm −2 for 3.5 nm thick oxide layers. Furthermore these different techniques are compared in detail. Concerning the volume traps, DLTS allows the determination of their energy location and capture cross-section. Such traps are found at 300 meV above the valence band. Complementary results on these traps are obtained by taking into account conductance technique measurements in the strong inversion regime.

Gate dielectric-dependent flicker noise in metal-oxide-semiconductor transistors

The paper presents low-frequency (flicker) noise measurements on n-channel metal-oxide-semiconductor transistors with TCE (trichoroethylene), dry, thermally nitrided, or reoxidized nitrided oxides as gate dielectrics. Results show that the noise level is lowest for conventional silicon oxide with TCE treatment and highest for thermally nitrided oxide. The frequency index (γ), which characterize a least-square fit of the noise spectrum in the frequency range of 10 Hz–5 kHz to the spectrum (∝f−γ), is not a constant, but fluctuates between 0.8 and 1.4 with the gate bias. In addition a trend is found that the higher the interface-state density at the midgap of silicon, the higher the noise level. But these two quantities are not in direct proportion to each other especially for the nitrided oxide device. All these observations lead to a unique implication: in addition to interface states, the oxide traps also contribute to the flicker noise generation. Our new observations also lend support to the past speculation that the carrier number fluctuation in the conduction channel is responsible for the noise generation. However, not all the noise parameters in the present study agree well with the general predictions of the existing flicker noise models.