Silicon-based devices are currently the most attractive group because they are functioning at room temperature and can be easily integrated into conventional silicon microelectronics. There are many models and simulation programs available to compute CV curves with quantum correction [Choi C-H, Wu Y, Goo JS, Yu Z, Dutton RW. IEEE Trans on Electron Devi 2000; 47(10): 1843; Croci S, Plossu C, Burignat S. J Mater Sci Mater Electron 2003; 14: 311; Soliman L, Duval E, Benzohra M, Lheurette E, Ketata K, Ketata M. Mater Sci Semicond Process 2001; 4: 163]. This work deals with the simulation of electron transfer through SiO 2 barrier of metal–oxide–semiconductor structure (MOS). The carrier density is given by a self consistent resolution of Schrödinger and Poisson equations and then the MOS capacitance is deduced and compared with results available in literature. As it is well known, the MOS capacitance–voltage profiling provides a simple determination of structure parameters. The extracted tunnel oxide thickness and substrate doping are compared with those used in the simulation. For the purpose to investigate the electron tunnelling through the barrier, we have used the transfer matrix approach. Using I– V simulations, we have shown that the traps in SiO 2 matrix have a drastic influence on electron tunnelling through the barrier. The trap-assisted contribution to the tunnelling current is included in many models [Maserjian J, Zamani N. J Appl Phys 1982; 53(1): 559; Houssa M, Stesmans A, Heyns MM. Semicond Sci Technol 2001; 16: 427; Aziz A, Kassmi K, Kassmi Ka, Olivie F. Semicond Sci Technol 2004; 19: 877; Wu You-Lin, Lin Shi-Tin. IEEE Trans Dev Mater Reliab 2006; 6(1): 75; Larcher L. IEEE Trans Electron Dev 2003; 50(5): 1246]; this is the basis for the interpretation of stress induced leakage current (SILC) and breakdown events. Memory effect becomes typical for this structure. We have studied the I– V dependence with trap parameters.