Silicon Metal Oxide Semiconductor Research Articles

Specific contact resistivity reduction in amorphous IGZO thin-film transistors through a TiN/IGTO heterogeneous interlayer

Oxide semiconductors have gained significant attention in electronic device industry due to their high potential for emerging thin-film transistor (TFT) applications. However, electrical contact properties such as specific contact resistivity (ρC) and width-normalized contact resistance (RCW) are significantly inferior in oxide TFTs compared to conventional silicon metal oxide semiconductor field-effect transistors. In this study, a multi-stack interlayer (IL) consisting of titanium nitride (TiN) and indium-gallium-tin-oxide (IGTO) is inserted between source/drain electrodes and amorphous indium-gallium-zinc-oxide (IGZO). The TiN is introduced to increase conductivity of the underlying layer, while IGTO acts as an n+-layer. Our findings reveal IGTO thickness (tIGTO)-dependent electrical contact properties of IGZO TFT, where ρC and RCW decrease as tIGTO increases to 8 nm. However, at tIGTO > 8 nm, they increase mainly due to IGTO crystallization-induced contact interface aggravation. Consequently, the IGZO TFTs with a TiN/IGTO (3/8 nm) IL reveal the lowest ρC and RCW of 9.0 × 10−6 Ω·cm2 and 0.7 Ω·cm, significantly lower than 8.0 × 10−4 Ω·cm2 and 6.9 Ω·cm in the TFTs without the IL, respectively. This improved electrical contact properties increases field-effect mobility from 39.9 to 45.0 cm2/Vs. This study demonstrates the effectiveness of this multi-stack IL approach in oxide TFTs.

Simulation study on quantum dot formation of double-qubit-Si-MOS device

Silicon quantum dots (QDs) are essential physical carriers of quantum bits (qubits) in quantum computing. However, their extremely small size renders them highly sensitive to both the fabrication process and surrounding environment. Accuracy and stability must be carefully considered. In this study, we propose a double gate QD device model based on silicon metal-oxide-semiconductor (Si-MOS) for the generation of spin qubits. Using a Technology Computer Aided Design (TCAD) simulation, we investigated the impact of device dimensions, including oxide layer thickness, channel length, and spacer length, on the QD structure. Additionally, we examined the effects of the temperature and interface trap concentration on QD formation. An equivalent circuit model was employed to assess the charging energy (Ec) of QDs. Our results demonstrate that by appropriately adjusting these parameters, it is possible to achieve a QD structure with a wide level spacing and small size capable of accommodating as few as four electrons. Furthermore, we calculated an Ec of 33 meV for the QDs.

Jellybean Quantum Dots in Silicon for Qubit Coupling and On‐Chip Quantum Chemistry (Adv. Mater. 19/2023)

Jellybean Quantum Dots Highly elliptical, elongated, quantum dots—so-called jellybean quantum dots—can be used for qubit–qubit coupling over short-to-intermediate distances and alleviate crowding in scaled-up quantum processors, as described by Zeheng Wang, Arne Laucht, and co-workers in article number 2208557. The cover illustration shows an artist's impression of two spin qubits in silicon metal–oxide–semiconductor quantum dots that are coupled through such a jellybean coupler.

Flopping-mode spin qubit in a Si-MOS quantum dot

Spin qubits based on silicon metal-oxide semiconductor (Si-MOS) quantum dots (QDs) are promising platforms for large-scale quantum computers. To control spin qubits in QDs, electric dipole spin resonance (EDSR) has been most commonly used in recent years. By delocalizing an electron across a double quantum dots charge state, “flopping-mode” EDSR has been realized in Si/SiGe QDs. Here, we demonstrate a flopping-mode spin qubit in a Si-MOS QD via Elzerman single-shot readout. When changing the detuning with a fixed drive power, we achieve s-shape spin resonance frequencies, an order of magnitude improvement in the spin Rabi frequencies, and virtually constant spin dephasing times. Our results offer a route to large-scale spin qubit systems with higher control fidelity in Si-MOS QDs.

Jellybean Quantum Dots in Silicon for Qubit Coupling and On-Chip Quantum Chemistry.

The small size and excellent integrability of silicon metal-oxide-semiconductor (SiMOS) quantum dot spin qubits make them an attractive system for mass-manufacturable, scaled-up quantum processors. Furthermore, classical control electronics can be integrated on-chip, in-between the qubits, if an architecture with sparse arrays of qubits is chosen. In such an architecture qubits are either transported across the chip via shuttling or coupled via mediating quantum systems over short-to-intermediate distances. This paper investigates the charge and spin characteristics of an elongated quantum dot-a so-called jellybean quantum dot-for the prospects of acting as a qubit-qubit coupler. Charge transport, charge sensing, and magneto-spectroscopy measurements are performed on a SiMOS quantum dot device at mK temperature and compared to Hartree-Fock multi-electron simulations. At low electron occupancies where disorder effects and strong electron-electron interaction dominate over the electrostatic confinement potential, the data reveals the formation of three coupled dots, akin to a tunable, artificial molecule. One dot is formed centrally under the gate and two are formed at the edges. At high electron occupancies, these dots merge into one large dot with well-defined spin states, verifying that jellybean dots have the potential to be used as qubit couplers in future quantum computingarchitectures.

Selective Sensing of Mixtures of Gases with CMOS-SOI-MEMS Sensor Dubbed GMOS

The need to achieve digital gas sensing technology, namely, a technology to sense and transmit gas-enabled digital media, has been recognized as highly challenging. This challenge has motivated the authors to focus on complementary metal oxide semiconductor silicon on insulator micro electro-mechanical system (CMOS-SOI-MEMS) technologies, and the result is a new pellistor-like sensor, dubbed GMOS, with integrated signal processing. In this study, we describe the performance of such sensors for the selective detection of mixtures of gases. The novel key ideas of this study are: (i) the use of the GMOS for gas sensing; (ii) applying the Kalman filter to improve the signal-to-noise ratio; (iii) adding artificial intelligence (AI) with tiny edge approach.

Low voltage AC electroluminescence in silicon MOS capacitors

Low power silicon based light source and detector are attractive for on-chip photonic circuits given their ease of process integration. However, conventional silicon light emitting diodes emit photons with energies near the band edge where the corresponding silicon photodetectors lack responsivity. On the other hand, previously reported hot carrier electroluminescent silicon devices utilizing a reverse biased diode require high operating voltages. Here, we investigate hot carrier electroluminescence in silicon metal–oxide–semiconductor capacitors operating under transient voltage conditions. During each voltage transient, large energy band bending is created at the edge of the source contact, much larger than what is achievable at a steady state. As a result, electrons and holes are injected efficiently from a single source contact into the silicon channel at the corresponding voltage transient, where they subsequently undergo impact ionization and phonon-assisted interband recombination. Notably, we show low voltage operation down to 2.8 V by using a 20 nm thick high-κ gate dielectric. We show further voltage scaling is possible by reducing the gate dielectric thickness, thus presenting a low voltage platform for silicon optoelectronic integrated circuits.

Valley Splitting in Silicon from the Interference Pattern of Quantum Oscillations.

We determine the energy splitting of the conduction-band valleys in two-dimensional electrons confined in silicon metal oxide semiconductor Hall-bar transistors. These silicon metal oxide semiconductor Hall bars are made by advanced semiconductor manufacturing on 300mm silicon wafers and support a two-dimensional electron gas of high quality with a maximum mobility of 17.6×10^{3} cm^{2}/Vs and minimum percolation density of 3.45×10^{10} cm^{-2}. Because of the low disorder, we observe beatings in the Shubnikov-de Haas oscillations that arise from the energy splitting of the two low-lying conduction band valleys. From the analysis of the oscillations beating patterns up to T=1.7 K, we estimate a maximum valley splitting of ΔE_{VS}=8.2 meV at a density of 6.8×10^{12} cm^{-2}. Furthermore, the valley splitting increases with density at a rate consistent with theoretical predictions for a near-ideal semiconductor-oxide interface.

Silicon Metal–Oxide–Semiconductor Transistor with a Dependent Pocket Contact and Two-Layer Polysilicon Gate

Silicon Metal–Oxide–Semiconductor Transistor with a Dependent Pocket Contact and Two-Layer Polysilicon Gate

Engineering local strain for single-atom nuclear acoustic resonance in silicon

Mechanical strain plays a key role in the physics and operation of nanoscale semiconductor systems, including quantum dots and single-dopant devices. Here, we describe the design of a nanoelectronic device, where a single nuclear spin is coherently controlled via nuclear acoustic resonance (NAR) through the local application of dynamical strain. The strain drives spin transitions by modulating the nuclear quadrupole interaction. We adopt an AlN piezoelectric actuator compatible with standard silicon metal–oxide–semiconductor processing and optimize the device layout to maximize the NAR drive. We predict NAR Rabi frequencies of order 200 Hz for a single 123Sb nucleus in a wide region of the device. Spin transitions driven directly by electric fields are suppressed in the center of the device, allowing the observation of pure NAR. Using electric field gradient-elastic tensors calculated by the density-functional theory, we extend our predictions to other high-spin group-V donors in silicon and to the isoelectronic 73Ge atom.

Ka-Band Stacked Power Amplifier Supporting 3GPP New Radio FR2 Band n258 Implemented Using 45 nm CMOS SOI

This paper presents a fully integrated, four-stack, single-ended, single stage power amplifier (PA) for millimeter-wave (mmWave) wireless applications that was fabricated and designed using 45 nm complementary metal oxide semiconductor silicon on insulator (CMOS SOI) technology. The frequency of operation is from 20 GHz to 30 GHz, with 13.7 dB of maximum gain. The maximum RF (radio frequency) output power (Pout), power-added efficiency (PAE) and output 1 dB compression point are 20.5 dBm, 29% and 18.8 dBm, respectively, achieved at 24 GHz. The error vector magnitude (EVM) of 12.5% was measured at an average channel power of 14.5 dBm at the center of the the 3GPP/NR (third generation partnership project/new radio) FR2 band n258—i.e., 26 GHz—using a 100 MHz 16-quadrature amplitude modulation (QAM) 3GPP/NR orthogonal frequency division modulation (OFDM) signal.

Highly stable Si MOSFET-type humidity sensor with ink-jet printed graphene quantum dots sensing layer

This paper investigates humidity sensing characteristics of a silicon metal oxide semiconductor field effect transistor (Si MOSFET)-based humidity sensor having horizontal floating-gate (FG) interdigitated with control-gate (CG). The sensing material of the humidity sensor is graphene quantum dots (GQDs), deposited locally on the interdigitated CG-FG area by an ink-jet printing method using a small amount of the GQDs solution. The humidity sensing characteristics of the sensor are measured as a parameter of relative humidity (RH). The response of the humidity sensor is 78 % to the humid air of 81.3 % RH. We also adopt a pulsed pre-bias method to improve the response and recovery characteristics of the humidity sensor. The response and recovery characteristics of the sensor can be improved 30 % and 40 % respectively by applying a pre-bias of 2 V and -1 V to the CG. In all relative humidity ranges, the FET-type humidity sensor has highly stable and reproducible characteristics in long-term measurements for 5 months.

Principles and impacts of dynamic threshold voltage in a p-GaN gate high-electron-mobility transistor

GaN power transistors are attracting increasing attention for next-generation power switching applications. However, GaN power transistors should not be regarded as a direct replacement for silicon power metal–oxide–semiconductor field-effect transistors, since the unique properties of GaN power transistors require special treatment. In this work we review a unique and critical property of GaN power transistors, the dynamic threshold voltage (V th). GaN power transistors feature a p-GaN gate structure, while the gate metal contacts the p-GaN layer through a Schottky junction. This unique p-GaN gate structure is distinctively different from the silicon metal–oxide–semiconductor gate structure in that the p-GaN layer is actually a floating region without direct electrical contact to the external electrodes of the device. The floating p-GaN layer enables a charge storage process during the switching operation of a p-GaN gate high-electron-mobility transistor. Through carefully designed experiments, the strong correlation between charge storage and the dynamic V th shift has been revealed; this also serves as an approach to accurately predict the dynamic V th during switching operation. The influence of the dynamic V th on power switching applications is discussed. For example, with a positive dynamic V th shift, the reverse conduction voltage of a GaN power transistor is significantly increased, adding to the power loss. This positive V th shift also demands a sufficiently high gate drive voltage to ensure that the GaN power transistor can be fully turned on, which reduces the safety margin for the gate reliability of the device. To design a GaN based power switching circuit, accurate simulation of the device/circuit characteristics is necessary. Circuit simulations that do not consider the dynamic V th lead to a large deviation from the measurement circuit characteristics. We demonstrate that by incorporating the dynamic V th into the circuit model this deviation can be effectively eliminated.

Developing Single Layer MOS Quantum Dots for Diagnostic Qubits.

The design, fabrication and characterization of single metal gate layer, metal-oxide-semiconductor (MOS) quantum dot devices robust against dielectric breakdown are presented as prototypes for future diagnostic qubits. These devices were developed as a preliminary solution to a longer term goal of a qubit platform for intercomparison between materials or for in-line diagnostics, and to provide a testbed for establishing classical measurements predictive of coherence performance. For this stage, we seek a robust MOS design that is compatible with wafer and chip architectures, that has a reduced process overhead and is sufficiently capable of challenging and advancing our measurement capabilities. In this report, we present our initial batch of silicon MOS devices using a single gate layer, which have not exhibited any failures with gate voltage excursions > 10 V, but do exhibit the reduced electrostatic control expected of a single gate layer design. We observe quantum dot formation, capacitive charge sensing between channels, and reasonable effective electron temperatures that enable spin qubit studies. The costs and benefits of the trade-off between device performance and fabrication efficiency will be discussed, as well as opportunities for future improvements.

Optimized Design of 1 MHz Intermediate Bus Converter Using GaN HEMT for Aerospace Applications

This paper presents the possibility of using Gallium Nitride (GaN) high-electron-mobility transistors (HEMTs) instead of the conventional silicon metal oxide semiconductor field effect transistor (MOSFET) to implement a high-frequency intermediate bus converter (IBC) as part of a typical distributed power architecture used in a space power application. The results show that processing the power at greater frequencies is possible with a reduction in mass and without impacting the system efficiency. The proposed solution was experimentally validated by the implementation of a 1 MHz zero-voltage and zero-current switching (ZVZCS) current-fed half-bridge converter with synchronous rectification compared with the same converter using silicon as the standard technology on power switches and working at 100 kHz. In conclusion, the replacement of silicon (Si) transistors by GaN HEMTs is feasible, and GaN HEMTs are promising next-generation devices in the power electronics field and can coexist with silicon semiconductors, mainly in some radiation-intensive environments, such as power space converters. The best physical properties of GaN HEMTs, such as inherent radiation hardness, low on resistance and parasitic capacitances, allow them to switch at higher frequencies with high efficiency achieving higher power density. We present an optimized design procedure to guaranty the zero-voltage switching condition that enables the power density to be increased without a penalization of the efficiency.

Nonlinear silicon photonics on CMOS-compatible tellurium oxide

Silicon photonics is coming of age; however, it is still lacking a monolithic platform for optical sources and nonlinear functionalities prompting heterogeneous integration of different materials tailored to different applications. Here we demonstrate tellurium oxide as a complementary metal oxide semiconductor silicon photonics platform for nonlinear functionalities, which is already becoming an established platform for sources and amplifiers. We show broadband supercontinuum generation covering the entire telecom window and show for the first time to our knowledge third-harmonic generation in its integrated embodiment. Together with the now-available lasers and amplifiers on integrated TeO 2 this work paves the way for a monolithic TeO 2 -based nonlinear silicon photonics platform.

Comparison of the Effects of Nonlinearities for Si MOSFET and GaN E-HEMT Based VSIs

Nonlinearities in voltage source inverters (VSIs) such as; dead time, switching time, delay time, voltage drops on the power switches, parasitic capacitance, etc., are considered to be the main sources of the output voltage distortions. These distortions result in low-order harmonics in the output current, which in turn increase core losses and create torque ripples. In particular, for low-speed applications with low-inductance motors, the control performance and the stability of the system degrades substantially, especially when the system operates in the low-torque region. In this work, the effects of these nonlinearities on the phase current and on the current control of the silicon (Si) metal oxide semiconductor field effect transistor (MOSFET) based VSI are investigated with an air cored low inductance permanent magnet synchronous motor. Furthermore, Gallium nitride (GaN) enhancement mode high electron mobility transistor (E-HEMT) based VSI is proposed to overcome this problem. Next, improvements in the current control process are demonstrated by comparing the experimental results obtained by using GaN E-HEMT and Si MOSFET based VSIs. Results show that GaN E-HEMT based VSI is a better choice for applications, which require a high bandwidth control.

Improving mobility of silicon metal-oxide–semiconductor devices for quantum dots by high vacuum activation annealing

To improve mobility of fabricated silicon metal-oxide–semiconductor (MOS) quantum devices, forming gas annealing is a common method used to mitigate the effects of disorder at the Si/SiO2 interface. However, the importance of activation annealing is usually ignored. Here, we show that a high vacuum environment for implantation activation is beneficial for improving mobility compared to nitrogen atmosphere. Low-temperature transport measurements of Hall bars show that peak mobility can be improved by a factor of two, reaching using high vacuum annealing during implantation activation. Moreover, the charge stability diagram of a single quantum dot is mapped, with no visible disturbance caused by disorder, suggesting the possibility of fabricating high-quality quantum dots on commercial wafers. Our results may provide valuable insights into device optimization in silicon-based quantum computing.

Quantum dot arrays in silicon and germanium

Electrons and holes confined in quantum dots define excellent building blocks for quantum emergence, simulation, and computation. Silicon and germanium are compatible with standard semiconductor manufacturing and contain stable isotopes with zero nuclear spin, thereby serving as excellent hosts for spins with long quantum coherence. Here, we demonstrate quantum dot arrays in a silicon metal-oxide-semiconductor (SiMOS), strained silicon (Si/SiGe), and strained germanium (Ge/SiGe). We fabricate using a multi-layer technique to achieve tightly confined quantum dots and compare integration processes. While SiMOS can benefit from a larger temperature budget and Ge/SiGe can make an Ohmic contact to metals, the overlapping gate structure to define the quantum dots can be based on a nearly identical integration. We realize charge sensing in each platform, for the first time in Ge/SiGe, and demonstrate fully functional linear and two-dimensional arrays where all quantum dots can be depleted to the last charge state. In Si/SiGe, we tune a quintuple quantum dot using the N + 1 method to simultaneously reach the few electron regime for each quantum dot. We compare capacitive crosstalk and find it to be the smallest in SiMOS, relevant for the tuning of quantum dot arrays. We put these results into perspective for quantum technology and identify industrial qubits, hybrid technology, automated tuning, and two-dimensional qubit arrays as four key trajectories that, when combined, enable fault-tolerant quantum computation.

Single-Shot Readout Performance of Two Heterojunction-Bipolar-Transistor Amplification Circuits at Millikelvin Temperatures

High-fidelity single-shot readout of spin qubits requires distinguishing states much faster than the T1 time of the spin state. One approach to improving readout fidelity and bandwidth (BW) is cryogenic amplification, where the signal from the qubit is amplified before noise sources are introduced and room-temperature amplifiers can operate at lower gain and higher BW. We compare the performance of two cryogenic amplification circuits: a current-biased heterojunction bipolar transistor circuit (CB-HBT), and an AC-coupled HBT circuit (AC-HBT). Both circuits are mounted on the mixing-chamber stage of a dilution refrigerator and are connected to silicon metal oxide semiconductor (Si-MOS) quantum dot devices on a printed circuit board (PCB). The power dissipated by the CB-HBT ranges from 0.1 to 1 μW whereas the power of the AC-HBT ranges from 1 to 20 μW. Referred to the input, the noise spectral density is low for both circuits, in the 15 to 30 fA/sqrt{{bf{Hz}}} range. The charge sensitivity for the CB-HBT and AC-HBT is 330 μe/sqrt{{bf{Hz}}} and 400 μe/sqrt{{bf{Hz}}}, respectively. For the single-shot readout performed, less than 10 μs is required for both circuits to achieve bit error rates below 10−3, which is a putative threshold for quantum error correction.