Silicon Germanium Technology Research Articles

W-band double-balanced down-conversion mixer with Marchand baluns in silicon-germanium technology

Presented is a monolithic W-band (75–110 GHz) down-conversion mixer consisting of a double-balanced core, Marchand-type on-chip baluns at inputs, and a two-stage output buffer, fabricated in a 200 GHz fT SiGe technology. Including the loss for input baluns, this mixer exhibits conversion gains of 14.4±2.8 dB and single sideband (SSB) noise figures of less than 19.5 dB across the entire W-band, drawing 28 mA from a 3.3 V supply.

A Fully Differential 77-GHz Active IQ Modulator in a Silicon-Germanium Technology

A 77-GHz IQ modulator in a fully differential circuit configuration is presented. It includes an local oscillation (LO) buffer amplifier, a medium-power output stage, a double-balanced active mixer architecture and on-chip baluns for easy characterization. A differential branch-line coupler provides quadrature phase signals at the upconversion mixer LO inputs. The circuit is manufactured in a 200-GHz transit frequency technology, and the circuit performance is shown by on-wafer measurements.

45 nm CMOS technology with low temperature selective epitaxy of SiGe

This paper describes the advanced embedded silicon germanium (eSiGe) technologies to apply the 45 nm node CMOS fabrication technology. There are three key techniques as follows. The first technique is a low temperature of epitaxial growth at 550 °C to suppress staking faults in eSiGe layer. The second one is a controlling of recess shape for eSiGe. Sigma(Σ)-shaped recess is applied, because the strain force on the channel of MOSFET is increased effectively by narrowing spacing between source and drain. The third one is to apply particular surface cleaning treatment before the epitaxial growth, to get the excellent SiGe crystallinity. We demonstrated the drain current of I on = 725 μA/μm and I off = 100 nA/μm for PMOSFET using above these techniques.

Silicon germanium based millimetre-wave ICs for Gbps wireless communications and radar systems

This paper establishes the viability and suitability of silicon germanium (SiGe8HP) technology, enablement tools and circuits to millimetre-wave applications today and a roadmap to the future. Key elements discussed include SiGe technology and design enablement advancements leading to the world's most highly integrated, lowest power 60 GHz transmitter/receiver ICs.

Guard rings: Structures, design methodology, integration, experimental results, and analysis for RF CMOS and RF mixed signal BiCMOS silicon germanium technology

This paper will first focus on the guard ring structures, design methodology, integration, experimental results and analysis. In this paper, the focus will be on test structure design issues, electrical characterization, and computer aided design (CAD) methodologies for advanced digital design, and mixed signal applications. The integration of “parameterized cell” guard ring structures concept into a Cadence™ based design methodology for the construction of electrostatic discharge (ESD) structures, I/O design, and latchup for radio frequency (RF) CMOS and Silicon Germanium technology will be discussed. The importance of the guard ring p-cell allows for evaluation of internal and external latchup, and the ability to verify the presence of the guard ring for whole chip design checking, verification and synthesis will be addressed. Additionally, this independent guard ring concept opens the door for a new methodology for RF design of primitive and hierarchical implementations.

Silicon transistor hits 500GHz performance

Low-cost silicon germanium technology is chasing indium phosphide heterojunction bipolar transistor performance. US researchers have pushed the cut-off frequency for SiGe HBTs to 500 GHz, but this is still about 200 GHz behind the best InP result so far.

A review of CMOS latchup and electrostatic discharge (ESD) in bipolar complimentary MOSFET (BiCMOS) Silicon Germanium technologies: Part II—Latchup

CMOS latchup and electrostatic discharge (ESD) continue to be a semiconductor quality and reliability area of interest as semiconductor components continue to be reduced to smaller dimensions. The combination of scaling, design integration, circuit performance objectives, new applications, and the evolving system environments, CMOS latchup and ESD robustness will continue to be a technology concern. With both the revolutionary and evolutionary changes in CMOS and Silicon Germanium semiconductor technologies, and changing product environments, new CMOS latchup and ESD requirements also continue in semiconductor design, device and chip-level simulation, design verification, chip-to-system evaluation, and the need for new latchup and ESD test specifications. Additionally, the issues of low cost, low power and radio frequency (RF) GHz performance objectives has lead to both revolutionary as well as derivative technologies; these have opened new doors for discovery, development and research in the area of latchup and ESD. Although latchup and ESD are not a new reliability arena, there are also new issues rising each year, making the latchup and ESD an area of continuous discovery, innovation and invention. In this paper, an introduction to latchup in CMOS and BiCMOS Silicon Germanium will be discussed.

A review of latchup and electrostatic discharge (ESD) in BiCMOS RF silicon germanium technologies: Part I—ESD

Electrostatic discharge (ESD) continues to be a semiconductor quality and reliability area of interest as semiconductor components are reduced to smaller dimensions. The combination of scaling, design integration, circuit performance objectives, new applications, and the evolving system environments, ESD robustness will continue to be a technology concern. With the transition from silicon bipolar junction transistor to modern BiCMOS silicon germanium (SiGe) semiconductor technologies, new semiconductor process and integration issues have evolved which influence both device performance and ESD protection. Additionally, the issues of low cost, low power and radio frequency (RF) GHz performance objectives has lead to both revolutionary as well as derivative technologies; these have opened new doors for discovery, development and research in the area of on-chip ESD protection and design. With the growth of interest of ESD in RF technology, new innovations and inventions are occurring at a rapid pace. In this paper, we will provide an introductory review of silicon germanium technology and ESD.

Ultracompact SOI CMOS frequency doubler for low power applications at 26.5-28.5 GHz

In this paper, a complementary metal oxide semiconductor (CMOS) frequency doubler for wireless applications at Ka-band is presented. The microwave monolithic integrated circuit (MMIC) is fabricated using digital 90 nm silicon on insulator (SOI) technology. All impedance matching, filter and bias elements are implemented on the chip, which has a very compact size of 0.37 mm/spl times/0.27 mm. At an output frequency of 27 GHz, source/load impedances of 50 /spl Omega/, a supply voltage of 1.25 V, a supply current of 8 mA and an input power of -4.5 dBm, a conversion gain of 1.5 dB was measured. To the knowledge of the authors, the circuit has by far the highest operation frequency for a CMOS frequency multiplier reported to date and requires lower supply power than circuits using leading edge III/V and silicon germanium (SiGe) technologies.

Ballistic Transport in SiGe and Strained-Si MOSFETs

We investigate the performance of bulk silicon and strained-silicon nanoscale MOSFETs in the ballistic regime, with the purpose of identifying possible advantages of silicon-germanium technology in devices approaching the ballistic regime. Investigation is performed with a 2D program that solves in a self-consistent way the Poisson equation, the Schrodinger equation with density functional theory, and the continuity equation for ballistic electrons. In the ballistic regime, when mobility has no physical meaning, strained-silicon FETs seem only to provide smaller short channel effects, but no improvement as far as transconductance and drive current are concerned.

An automated design system methodology and strategy for electrostatic discharge protection circuits in RF CMOS and BiCMOS silicon germanium technology

In a Cadence environment, a novel automated methodology is established to optimize (electrostatic discharge) ESD networks. An automated ESD design system for digital, analog and radio frequency (RF) circuits in a mixed signal semiconductor chips using a hierarchy of RF-characterized higher order graphical parameterized cells allows for co-synthesis of RF design and ESD evaluation. The auto-generated ESD design system includes CMOS and BiCMOS input, rail-to-rail and power clamp ESD network with layout, schematic and symbolic representations. Human body model (HBM), machine model (MM), and transmission line pulse (TLP) results demonstrate the operation of the ESD designs, and the region of optimum ESD results.

Deep submicron CMOS based on silicon germanium technology

The advantages to be gained by using SiGe in CMOS technology are examined, Conventional MOSFETs are compared with SiGe heterojunction MOSFETs suitable for CMOS technology and having channel lengths between 0.5 and 0.1 /spl mu/m. Two-dimensional computer simulation demonstrates that the improved mobility in the SiGe devices, due to higher bulk mobility and the elimination of Si/SiO/sub 2/ interface scattering by the inclusion of a capping layer, results in significant velocity overshoot close to the source-end of the channel. The cut-off frequency, f/sub t/, is found to increase by around 50% for n-channel devices while more than doubling for p-channel devices for typical estimates of mobility. The results offer the prospect of a more balanced CMOS and improved circuit speed especially when using dynamic logic.

Recent advances in silicon-germanium alloy technology and an assessment of the problems of building the modules for a radioisotope thermo-electric generator

This paper reviews the state of the art of silicon-germanium technology and assesses the problems of building thermoelectric modules in Europe, based upon silicon-germanium alloys, for use in a multihundred watt radioisotope thermoelectric generator. The generator developed in the United States for the International Solar Polar mission has been used as a reference system. The essential features of an alternative system, which employs thermocouples fabricated from improved silicon-germanium alloys based upon a design by the Fairchild Space and Electronics Company, is also described. It is concluded that although the fabrication of reliable electrical contacts will present a major problem, the technology is available in Europe to build thermoelectric modules similar to those developed for the International Solar Polar mission.